Patch to add support for more NEC VR targets [opcodes]

[Nick Clifton]

Hi Richard,

> 2002-09-27  Gavin Romig-Koch  <gavin@redhat.com>
>             Ken Raeburn  <raeburn@cygnus.com>
>             Aldy Hernandez  <aldyh@redhat.com>
>             Eric Christopher  <echristo@redhat.com>
>             Richard Sandiford  <rsandifo@redhat.com>
> 
> [include/opcode/]
> 	* mips.h: Update comment for new opcodes.
> 	(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
> 	(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
> 	(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
> 	(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
> 	(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
> 	Don't match CPU_R4111 with INSN_4100.
> 
> [opcodes/]
> 	* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
> 	(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
> 	and bfd_mach_mips5500.
> 	* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
> 	(N411, N412, N5, N54, N55): New convenience defines.
> 	(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
> 	Change dmadd16 and madd16 from V1 to N411.

Approved - please apply - but ...

> +/* NEC VR4111/VR4181 instruction. */
> +#define INSN_4111                 0x00400000
> +/* NEC VR4120 instruction. */

Please fix formatting of comments.

Cheers
        Nick