[binutils-gdb] RISC-V: Add support for XAndesVPackFPH extension
Kuan-Lin Chen
kuanlinchen@sourceware.org
Tue Sep 1 03:04:44 GMT 2026
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f58993d5fbdfb7c5033adf483a1abed66f315ceb
commit f58993d5fbdfb7c5033adf483a1abed66f315ceb
Author: Ethan Y. C. Liang <ycl669@andestech.com>
Date: Tue Nov 18 17:13:47 2025 +0800
RISC-V: Add support for XAndesVPackFPH extension
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesVPackFPH extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesVPackFPH as an additional ISA extension
for Andes.
* testsuite/gas/riscv/march-help.l: Add xandesvpackfph string.
* testsuite/gas/riscv/x-andes-vpackfph.d: New test.
* testsuite/gas/riscv/x-andes-vpackfph.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESVPACKFPH
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add vector packed FP16 fused multiply-add
instructions.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
Diff:
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-vpackfph.d | 14 ++++++++++++++
gas/testsuite/gas/riscv/x-andes-vpackfph.s | 5 +++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 43 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 39399c32bcb..cb228c4ba1b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1655,6 +1655,7 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xandesbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvsintload", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
+ {"xandesvpackfph", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -3095,6 +3096,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xandesvbfhcvt");
case INSN_CLASS_XANDESVSINTLOAD:
return riscv_subset_supports (rps, "xandesvsintload");
+ case INSN_CLASS_XANDESVPACKFPH:
+ return riscv_subset_supports (rps, "xandesvpackfph");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3447,6 +3450,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xandesvbfhcvt";
case INSN_CLASS_XANDESVSINTLOAD:
return "xandesvsintload";
+ case INSN_CLASS_XANDESVPACKFPH:
+ return "xandesvpackfph";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 9a7be7a6ee7..90b67841271 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -781,6 +781,11 @@ The XAndesVSIntLoad extension provides vector load instructions for INT4 data in
It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+@item XAndesVPackFPH
+The XAndesVPackFPH extension provides vector packed FP16 fused multiply-add instructions.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index e8f0abcb10c..add55de69fe 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -170,6 +170,7 @@ All available -march extensions for RISC-V:
xandesbfhcvt 5.0
xandesvbfhcvt 5.0
xandesvsintload 5.0
+ xandesvpackfph 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-vpackfph.d b/gas/testsuite/gas/riscv/x-andes-vpackfph.d
new file mode 100644
index 00000000000..693c486048a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vpackfph.d
@@ -0,0 +1,14 @@
+#as: -march=rv32i_xandesvpackfph
+#source: x-andes-vpackfph.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0a86425b[ ]+nds\.vfpmadt\.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+0886425b[ ]+nds\.vfpmadt\.vf[ ]+v4,fa2,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+0e86425b[ ]+nds\.vfpmadb\.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+0c86425b[ ]+nds\.vfpmadb\.vf[ ]+v4,fa2,v8,v0\.t
diff --git a/gas/testsuite/gas/riscv/x-andes-vpackfph.s b/gas/testsuite/gas/riscv/x-andes-vpackfph.s
new file mode 100644
index 00000000000..67214aee48a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vpackfph.s
@@ -0,0 +1,5 @@
+target:
+ nds.vfpmadt.vf v4, fa2, v8
+ nds.vfpmadt.vf v4, fa2, v8, v0.t
+ nds.vfpmadb.vf v4, fa2, v8
+ nds.vfpmadb.vf v4, fa2, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 8e0a21db6f5..536570f2469 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2616,6 +2616,11 @@
#define MASK_NDS_VLN8_V 0xfdf0707f
#define MATCH_NDS_VLNU8_V 0x430405b
#define MASK_NDS_VLNU8_V 0xfdf0707f
+/* Vendor-specific (Andes) XAndesVPackFPH instructions. */
+#define MATCH_NDS_VFPMADT_VF 0x800405b
+#define MASK_NDS_VFPMADT_VF 0xfc00707f
+#define MATCH_NDS_VFPMADB_VF 0xc00405b
+#define MASK_NDS_VFPMADB_VF 0xfc00707f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -5067,6 +5072,9 @@ DECLARE_INSN(nds_vfncvt_bf16_s, MATCH_NDS_VFNCVT_BF16_S, MASK_NDS_VFNCVT_BF16_S)
/* Vendor-specific (Andes) XAndesVSIntLoad instructions. */
DECLARE_INSN(nds_vln8_v, MATCH_NDS_VLN8_V, MASK_NDS_VLN8_V)
DECLARE_INSN(nds_vlnu8_v, MATCH_NDS_VLNU8_V, MASK_NDS_VLNU8_V)
+/* Vendor-specific (Andes) XAndesVPackFPH instructions. */
+DECLARE_INSN(nds_vfpmadt_vf, MATCH_NDS_VFPMADT_VF, MASK_NDS_VFPMADT_VF)
+DECLARE_INSN(nds_vfpmadb_vf, MATCH_NDS_VFPMADB_VF, MASK_NDS_VFPMADB_VF)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index a5f565898c7..9b30b0af7d9 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -609,6 +609,7 @@ enum riscv_insn_class
INSN_CLASS_XANDESBFHCVT,
INSN_CLASS_XANDESVBFHCVT,
INSN_CLASS_XANDESVSINTLOAD,
+ INSN_CLASS_XANDESVPACKFPH,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bbbfa1eeb4f..b5ab18238ee 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2361,6 +2361,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"nds.vln8.v", 0, INSN_CLASS_XANDESVSINTLOAD, "Vd,0(s)Vm", MATCH_NDS_VLN8_V, MASK_NDS_VLN8_V, match_opcode, INSN_DREF},
{"nds.vlnu8.v", 0, INSN_CLASS_XANDESVSINTLOAD, "Vd,0(s)Vm", MATCH_NDS_VLNU8_V, MASK_NDS_VLNU8_V, match_opcode, INSN_DREF},
+/* Vendor-specific (Andes) XAndesVPackFPH instructions. */
+{"nds.vfpmadt.vf", 0, INSN_CLASS_XANDESVPACKFPH, "Vd,S,VtVm", MATCH_NDS_VFPMADT_VF, MASK_NDS_VFPMADT_VF, match_opcode, 0},
+{"nds.vfpmadb.vf", 0, INSN_CLASS_XANDESVPACKFPH, "Vd,S,VtVm", MATCH_NDS_VFPMADB_VF, MASK_NDS_VFPMADB_VF, match_opcode, 0},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
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