[binutils-gdb] aarch64: Add support for TEV instructions
SRINATH PARVATHANENI
sripar01@sourceware.org
Mon Jan 5 17:51:38 GMT 2026
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=859d7ccd9f9b1c995df4e74b227f141405cae842
commit 859d7ccd9f9b1c995df4e74b227f141405cae842
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Mon Jan 5 17:50:43 2026 +0000
aarch64: Add support for TEV instructions
This patch adds support for FEAT_TEV feature enabled by "+tev"
flag along with support for following instructions.
* TENTER
* TEXIT
TENTER instruction uses the existing AARCH64_OPND_NOT_BALANCED_17 operand
to handle the not_balanced (NB) argument , where as a new operand
AARCH64_OPND_NOT_BALANCED_10 is added to support the NB (not_balanced)
argument in TEXIT instruction.
Diff:
---
gas/config/tc-aarch64.c | 10 ++++++-
gas/doc/c-aarch64.texi | 2 ++
gas/testsuite/gas/aarch64/tev-invalid-1.d | 4 +++
gas/testsuite/gas/aarch64/tev-invalid-1.l | 18 +++++++++++++
gas/testsuite/gas/aarch64/tev-invalid-1.s | 22 ++++++++++++++++
gas/testsuite/gas/aarch64/tev-invalid-2.d | 4 +++
gas/testsuite/gas/aarch64/tev-invalid-2.l | 22 ++++++++++++++++
gas/testsuite/gas/aarch64/tev.d | 30 +++++++++++++++++++++
gas/testsuite/gas/aarch64/tev.s | 28 ++++++++++++++++++++
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-asm-2.c | 1 +
opcodes/aarch64-dis-2.c | 43 +++++++++++++++++++++++--------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 1 +
opcodes/aarch64-tbl-2.h | 2 ++
opcodes/aarch64-tbl.h | 11 ++++++++
16 files changed, 190 insertions(+), 12 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 97029ade890..12f27be530e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6437,6 +6437,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
operand->hint_option = aarch64_hint_options + default_value;
break;
+ case AARCH64_OPND_NOT_BALANCED_10:
case AARCH64_OPND_NOT_BALANCED_17:
operand->imm.value = default_value;
break;
@@ -8188,6 +8189,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->barrier = aarch64_barrier_dsb_nxs_options + val;
break;
+ case AARCH64_OPND_NOT_BALANCED_10:
case AARCH64_OPND_NOT_BALANCED_17:
{
char *p = str;
@@ -8196,11 +8198,16 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if ((strncasecmp (p, "nb", 2) == 0) && (str == p + 2))
info->imm.value = 1;
+ /* Optional argument is absent in the first operand position, fail
+ without updating backtrack_pos so that the default operand value
+ is applied. */
+ else if (i == 0 && p == str)
+ goto failure;
else
{
- set_default_error ();
/* Turn off backtrack as this optional operand is present. */
backtrack_pos = 0;
+ set_default_error ();
goto failure;
}
break;
@@ -10852,6 +10859,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
{"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
{"poe2", AARCH64_FEATURE (POE2), AARCH64_NO_FEATURES},
+ {"tev", AARCH64_FEATURE (TEV), AARCH64_NO_FEATURES},
{"aes", AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)},
{"sm4", AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)},
{"sha3", AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 808acc6db57..c4e217f9fc5 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -381,6 +381,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Translation Hardening Extension.
@item @code{tme} @tab
@tab Enable the Transactional Memory Extension.
+@item @code{tev} @tab
+ @tab TIndex Exception-like Vector Extension.
@item @code{wfxt} @tab
@tab Enable @code{wfet} and @code{wfit} instructions.
@item @code{xs} @tab
diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.d b/gas/testsuite/gas/aarch64/tev-invalid-1.d
new file mode 100644
index 00000000000..f6a659e5888
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev-invalid-1.d
@@ -0,0 +1,4 @@
+#name: Invalid tev instructions.
+#source: tev-invalid-1.s
+#as: -march=armv8-a+tev
+#error_output: tev-invalid-1.l
diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.l b/gas/testsuite/gas/aarch64/tev-invalid-1.l
new file mode 100644
index 00000000000..3dc19072b0c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev-invalid-1.l
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #-10'
+.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #128'
+.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #3111'
+.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #777'
+.*: Error: constant expression required at operand 1 -- `tenter nb,#127'
+.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #-10,nb'
+.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #777,nb'
+.*: Error: operand 2 must be an optional not balanced indicator \(NB\) -- `tenter #15,nbb'
+.*: Error: unexpected characters following instruction at operand 2 -- `tenter #15,nb,nb'
+.*: Error: comma expected between operands at operand 2 -- `tenter #31 NB'
+.*: Error: immediate operand required at operand 1 -- `tenter x10,#127'
+.*: Error: constant expression required at operand 1 -- `tenter NB,#128'
+.*: Error: operand 1 must be an optional not balanced indicator \(NB\) -- `texit x0'
+.*: Error: operand 1 must be an optional not balanced indicator \(NB\) -- `texit #10'
+.*: Error: operand 1 must be an optional not balanced indicator \(NB\) -- `texit n'
+.*: Error: operand 1 must be an optional not balanced indicator \(NB\) -- `texit nN'
+.*: Error: operand 1 must be an optional not balanced indicator \(NB\) -- `texit x0,nb'
diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.s b/gas/testsuite/gas/aarch64/tev-invalid-1.s
new file mode 100644
index 00000000000..b9f583b310a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev-invalid-1.s
@@ -0,0 +1,22 @@
+#TENTER instructions
+ tenter #-10
+ tenter #128
+ tenter #3111
+ tenter #777
+ tenter nb, #127
+
+#TENTER instructions with not_balanced
+ tenter #-10, nb
+ tenter #777, nb
+ tenter #15, nbb
+ tenter #15, nb,nb
+ tenter #31 NB
+ tenter x10, #127
+ tenter NB, #128
+
+#TEXIT instructions
+ texit x0
+ texit #10
+ texit n
+ texit nN
+ texit x0, nb
diff --git a/gas/testsuite/gas/aarch64/tev-invalid-2.d b/gas/testsuite/gas/aarch64/tev-invalid-2.d
new file mode 100644
index 00000000000..6d5c9c1b9aa
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev-invalid-2.d
@@ -0,0 +1,4 @@
+#name: TENTER and TEXIT instructions without +tev flag.
+#source: tev.s
+#as: -march=armv8-a
+#error_output: tev-invalid-2.l
diff --git a/gas/testsuite/gas/aarch64/tev-invalid-2.l b/gas/testsuite/gas/aarch64/tev-invalid-2.l
new file mode 100644
index 00000000000..c220dca9097
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev-invalid-2.l
@@ -0,0 +1,22 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support `tenter #0'
+.*: Error: selected processor does not support `tenter #1'
+.*: Error: selected processor does not support `tenter #3'
+.*: Error: selected processor does not support `tenter #7'
+.*: Error: selected processor does not support `tenter #15'
+.*: Error: selected processor does not support `tenter #31'
+.*: Error: selected processor does not support `tenter #63'
+.*: Error: selected processor does not support `tenter #127'
+.*: Error: selected processor does not support `tenter #0,nb'
+.*: Error: selected processor does not support `tenter #1,nb'
+.*: Error: selected processor does not support `tenter #3,nb'
+.*: Error: selected processor does not support `tenter #7,nb'
+.*: Error: selected processor does not support `tenter #15,nb'
+.*: Error: selected processor does not support `tenter #31,NB'
+.*: Error: selected processor does not support `tenter #63,nb'
+.*: Error: selected processor does not support `tenter #127,NB'
+.*: Error: selected processor does not support `texit'
+.*: Error: selected processor does not support `texit nb'
+.*: Error: selected processor does not support `texit NB'
+.*: Error: selected processor does not support `texit nB'
+.*: Error: selected processor does not support `texit Nb'
diff --git a/gas/testsuite/gas/aarch64/tev.d b/gas/testsuite/gas/aarch64/tev.d
new file mode 100644
index 00000000000..d5f4dabfd63
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev.d
@@ -0,0 +1,30 @@
+#objdump: -dr
+#as: -march=armv8-a+tev
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: d4e00000 tenter #0x0
+.*: d4e00020 tenter #0x1
+.*: d4e00060 tenter #0x3
+.*: d4e000e0 tenter #0x7
+.*: d4e001e0 tenter #0xf
+.*: d4e003e0 tenter #0x1f
+.*: d4e007e0 tenter #0x3f
+.*: d4e00fe0 tenter #0x7f
+.*: d4e20000 tenter #0x0, nb
+.*: d4e20020 tenter #0x1, nb
+.*: d4e20060 tenter #0x3, nb
+.*: d4e200e0 tenter #0x7, nb
+.*: d4e201e0 tenter #0xf, nb
+.*: d4e203e0 tenter #0x1f, nb
+.*: d4e207e0 tenter #0x3f, nb
+.*: d4e20fe0 tenter #0x7f, nb
+.*: d6ff03e0 texit
+.*: d6ff07e0 texit nb
+.*: d6ff07e0 texit nb
+.*: d6ff07e0 texit nb
+.*: d6ff07e0 texit nb
diff --git a/gas/testsuite/gas/aarch64/tev.s b/gas/testsuite/gas/aarch64/tev.s
new file mode 100644
index 00000000000..c7d3c308025
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tev.s
@@ -0,0 +1,28 @@
+#TENTER instruction
+ tenter #0
+ tenter #1
+ tenter #3
+ tenter #7
+ tenter #15
+ tenter #31
+ tenter #63
+ tenter #127
+
+#TENTER instruction with not_balanced
+ tenter #0, nb
+ tenter #1, nb
+ tenter #3, nb
+ tenter #7, nb
+ tenter #15, nb
+ tenter #31, NB
+ tenter #63, nb
+ tenter #127, NB
+
+#TEXIT instruction
+ texit
+
+#TEXIT instruction with not_balanced
+ texit nb
+ texit NB
+ texit nB
+ texit Nb
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7797b1812a4..5f840a44ad6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -281,6 +281,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE_B16MM,
/* POE2 instructions. */
AARCH64_FEATURE_POE2,
+ /* TEV instructions. */
+ AARCH64_FEATURE_TEV,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
@@ -693,6 +695,7 @@ enum aarch64_opnd
AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
+ AARCH64_OPND_NOT_BALANCED_10, /* an optional not balanced indicator (NB). */
AARCH64_OPND_NOT_BALANCED_17, /* an optional not balanced indicator (NB). */
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
each condition flag. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 8d0a963513b..85e01ac76ae 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -930,6 +930,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case AARCH64_OPND_UNDEFINED:
case AARCH64_OPND_CCMP_IMM:
case AARCH64_OPND_SIMM5:
+ case AARCH64_OPND_NOT_BALANCED_10:
case AARCH64_OPND_NOT_BALANCED_17:
case AARCH64_OPND_NZCV:
case AARCH64_OPND_ADDR_PCREL9:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index d4c95d4b81e..c00b9b309b1 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -26665,10 +26665,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 11010100x11xxxxxxxxxxxxxxxx0xx00. */
- return A64_OPID_d4600000_tcancel_TME_UIMM16;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 11010100011xxxxxxxxxxxxxxxx0xx00. */
+ return A64_OPID_d4600000_tcancel_TME_UIMM16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 11010100111xxxxxxxxxxxxxxxx0xx00. */
+ return A64_OPID_d4e00000_tenter_UIMM7_NOT_BALANCED_17;
+ }
}
}
}
@@ -26760,19 +26770,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10101100x1xxxxxxxxxxxxxxxx0xxxx. */
- return A64_OPID_d63f0000_blr_Rn;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010110001xxxxxxxxxxxxxxxx0xxxx. */
+ return A64_OPID_d63f0000_blr_Rn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010110101xxxxxxxxxxxxxxxx0xxxx. */
+ return A64_OPID_d6bf03e0_drps;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10101101x1xxxxxxxxxxxxxxxx0xxxx. */
- return A64_OPID_d6bf03e0_drps;
+ x1010110x11xxxxxxxxxxxxxxxx0xxxx. */
+ return A64_OPID_d6ff03e0_texit_NOT_BALANCED_10;
}
}
}
@@ -37887,6 +37907,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case AARCH64_OPND_UNDEFINED:
case AARCH64_OPND_CCMP_IMM:
case AARCH64_OPND_SIMM5:
+ case AARCH64_OPND_NOT_BALANCED_10:
case AARCH64_OPND_NOT_BALANCED_17:
case AARCH64_OPND_NZCV:
case AARCH64_OPND_ADDR_ADRP:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 7619723aae1..15f76f685ea 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -104,6 +104,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_0}, "a 16-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10}, "an optional not balanced indicator (NB)"},
{AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1}, "an optional not balanced indicator (NB)"},
{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
{AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 6b3ecf2e138..09d0b410fee 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5162,6 +5162,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s", style_sub_mnem (styler, "dsync"));
break;
+ case AARCH64_OPND_NOT_BALANCED_10:
case AARCH64_OPND_NOT_BALANCED_17:
if (opnd->imm.value)
snprintf (buf, size, "%s", style_sub_mnem (styler, "nb"));
diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index 8fcf7feb978..fbab04e40de 100644
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -4048,5 +4048,7 @@ enum aarch64_opcode_idx
A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED_17,
A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED_17,
A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED_17,
+ A64_OPID_d4e00000_tenter_UIMM7_NOT_BALANCED_17,
+ A64_OPID_d6ff03e0_texit_NOT_BALANCED_10,
A64_OPID_MAX,
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 613300a75b1..3af6e1dcf3a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3100,6 +3100,8 @@ static const aarch64_feature_set aarch64_feature_sve_b16mm =
AARCH64_FEATURE (SVE_B16MM);
static const aarch64_feature_set aarch64_feature_POE2 =
AARCH64_FEATURE (POE2);
+static const aarch64_feature_set aarch64_feature_tev =
+ AARCH64_FEATURE (TEV);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -3235,6 +3237,7 @@ static const aarch64_feature_set aarch64_feature_POE2 =
#define F16MM_SVE2p2 &aarch64_feature_f16mm_sve2p2
#define SVE_B16MM &aarch64_feature_sve_b16mm
#define POE2 &aarch64_feature_POE2
+#define TEV &aarch64_feature_tev
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
@@ -3591,6 +3594,8 @@ static const aarch64_feature_set aarch64_feature_POE2 =
{ NAME, OPCODE, MASK, CLASS, 0, SVE_B16MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL }
#define POE2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS, FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, POE2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
+#define TEV_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS, FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, TEV, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -7903,6 +7908,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
POE2_INSN("tchangeb", 0xd5840000, 0xfffdfc00, aarch64_misc, OP3 (Rd, Rn, NOT_BALANCED_17), QL_X2NIL, F_OPD2_OPT | F_DEFAULT (0x0)),
POE2_INSN("tchangeb", 0xd5940000, 0xfffdf000, aarch64_misc, OP3 (Rd, UIMM7, NOT_BALANCED_17), QL_X1NIL2, F_OPD2_OPT | F_DEFAULT (0x0)),
+ /* TEV instructions. */
+ TEV_INSN("tenter", 0xd4e00000, 0xfffdf01f, aarch64_misc, OP2 (UIMM7, NOT_BALANCED_17), QL_PRFM_PCREL, F_OPD1_OPT | F_DEFAULT (0x0)),
+ TEV_INSN("texit", 0xd6ff03e0, 0xfffffbff, aarch64_misc, OP1 (NOT_BALANCED_10), {}, F_OPD0_OPT | F_DEFAULT (0x0)),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -8055,6 +8064,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a 5-bit unsigned immediate") \
Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \
"a 5-bit signed immediate") \
+ Y(IMMEDIATE, imm, "NOT_BALANCED_10", 0, F(FLD_imm1_10), \
+ "an optional not balanced indicator (NB)") \
Y(IMMEDIATE, imm, "NOT_BALANCED_17", 0, F(FLD_imm17_1), \
"an optional not balanced indicator (NB)") \
Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \
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