[binutils-gdb] aarch64: Add support for FEAT_SME_B16B16 feature.
SRINATH PARVATHANENI
sripar01@sourceware.org
Fri Jan 10 16:48:23 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=308d7670f038de523d5ecbb06e05446a798c36dc
commit 308d7670f038de523d5ecbb06e05446a798c36dc
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Fri Jan 10 16:47:32 2025 +0000
aarch64: Add support for FEAT_SME_B16B16 feature.
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions,
under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16".
FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that
"+sme-b16b16" enables "+sme2" and "+sve-b16b16".
Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*.
eg: sme-b16b16-1.s, sme-b16b16-1.d.
The spec for this feature and instructions is availabe here [1]:
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
Diff:
---
gas/NEWS | 3 +
gas/config/tc-aarch64.c | 2 +
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/sme-b16b16-1.d | 126 ++++
gas/testsuite/gas/aarch64/sme-b16b16-1.s | 143 +++++
gas/testsuite/gas/aarch64/sme-b16b16-bad-1.d | 3 +
gas/testsuite/gas/aarch64/sme-b16b16-bad-1.l | 193 +++++++
gas/testsuite/gas/aarch64/sme-b16b16-bad-1.s | 173 ++++++
include/opcode/aarch64.h | 2 +
opcodes/aarch64-dis-2.c | 820 +++++++++++++++++----------
opcodes/aarch64-tbl.h | 26 +
11 files changed, 1182 insertions(+), 311 deletions(-)
diff --git a/gas/NEWS b/gas/NEWS
index be4afb65fa3..5c8975dbc44 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -2,6 +2,9 @@
* Add support for the x86 Zhaoxin PadLock RNG2 instruction.
+* Add support for AArch64 SME and SVE non-widening BFloat16 (SVE_B16B16 and
+ SME_B16B16) instructions.
+
* Add support for the x86 Intel AVX10.2 instructions.
* Add support for the x86 Intel SM4 AVX10.2 instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b019ea32dcf..fc8fcb07a78 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10764,6 +10764,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
AARCH64_FEATURE (SME_F8F32)},
{"sme-f16f16", AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME2)},
+ {"sme-b16b16", AARCH64_FEATURE (SME_B16B16),
+ AARCH64_FEATURES (2, SVE_B16B16, SME2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index fc14e5173b0..e75995323e9 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -269,6 +269,8 @@ automatically cause those extensions to be disabled.
@tab Enable the SM3 and SM4 cryptographic extensions.
@item @code{sme} @tab @code{sve2}, @code{bf16}
@tab Enable the Scalable Matrix Extension.
+@item @code{sme-b16b16} @tab @code{sme2}, @code{sve-b16b16}
+ @tab Enable SME ZA-targeting non-widening BFloat16 instructions.
@item @code{sme-f8f16} @tab @code{sme-f8f32}
@tab Enable the SME F8F16 Extension.
@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
diff --git a/gas/testsuite/gas/aarch64/sme-b16b16-1.d b/gas/testsuite/gas/aarch64/sme-b16b16-1.d
new file mode 100644
index 00000000000..806b862f6c4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-b16b16-1.d
@@ -0,0 +1,126 @@
+#name: Test of SME2 non-widening BFloat16 instructions.
+#as: -march=armv8-a+sme-b16b16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c1e41c00 bfadd za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e47c00 bfadd za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41c07 bfadd za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41fc0 bfadd za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e41fc3 bfadd za.h\[w8, 3, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e51c00 bfadd za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e57c00 bfadd za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51c07 bfadd za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51f80 bfadd za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}
+.*: c1e51f83 bfadd za.h\[w8, 3, vgx4\], { ?z28.h-z31.h ?}
+.*: c1e41c08 bfsub za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e47c08 bfsub za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41c0f bfsub za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41fc8 bfsub za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e41fcb bfsub za.h\[w8, 3, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e51c08 bfsub za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e57c08 bfsub za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51c0f bfsub za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51f88 bfsub za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}
+.*: c1e51f8b bfsub za.h\[w8, 3, vgx4\], { ?z28.h-z31.h ?}
+.*: c1101020 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1107020 bfmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1101027 bfmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c11013e0 bfmla za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, z0.h\[0\]
+.*: c11f1020 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h\[0\]
+.*: c1101c28 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1101428 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[3\]
+.*: c1101c2b bfmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1109020 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c110f020 bfmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109027 bfmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c11093a0 bfmla za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, z0.h\[0\]
+.*: c11f9020 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h\[0\]
+.*: c1109c28 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1109428 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[3\]
+.*: c1109c2b bfmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1601c00 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1607c00 bfmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601c07 bfmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601fe0 bfmla za.h\[w8, 0, vgx2\], { ?z31.h-z0.h ?}, z0.h
+.*: c16f1c00 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c16f1c03 bfmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c1701c00 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1707c00 bfmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701c07 bfmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701fe0 bfmla za.h\[w8, 0, vgx4\], { ?z31.h-z2.h ?}, z0.h
+.*: c17f1c00 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c17f1c03 bfmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c1e01008 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e07008 bfmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e0100f bfmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e013c8 bfmla za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, { ?z0.h-z1.h ?}
+.*: c1fe1008 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1fe100b bfmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1e11008 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e17008 bfmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e1100f bfmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e11388 bfmla za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, { ?z0.h-z3.h ?}
+.*: c1fd1008 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1fd100b bfmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1101030 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1107030 bfmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1101037 bfmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c11013f0 bfmls za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, z0.h\[0\]
+.*: c11f1030 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h\[0\]
+.*: c1101c38 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1101438 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[3\]
+.*: c1101c3b bfmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1109030 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c110f030 bfmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109037 bfmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c11093b0 bfmls za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, z0.h\[0\]
+.*: c11f9030 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h\[0\]
+.*: c1109c38 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1109438 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[3\]
+.*: c1109c3b bfmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1601c08 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1607c08 bfmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601c0f bfmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601fe8 bfmls za.h\[w8, 0, vgx2\], { ?z31.h-z0.h ?}, z0.h
+.*: c16f1c08 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c16f1c0b bfmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c1701c08 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1707c08 bfmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701c0f bfmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701fe8 bfmls za.h\[w8, 0, vgx4\], { ?z31.h-z2.h ?}, z0.h
+.*: c17f1c08 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c17f1c0b bfmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c1e01018 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e07018 bfmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e0101f bfmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e013d8 bfmls za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, { ?z0.h-z1.h ?}
+.*: c1fe1018 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1fe101b bfmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1e11018 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e17018 bfmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e1101f bfmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e11398 bfmls za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, { ?z0.h-z3.h ?}
+.*: c1fd1018 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1fd101b bfmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: 81a00008 bfmopa za0.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a00009 bfmopa za1.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a01c08 bfmopa za0.h, p7/m, p0/m, z0.h, z0.h
+.*: 81a0e008 bfmopa za0.h, p0/m, p7/m, z0.h, z0.h
+.*: 81a003e8 bfmopa za0.h, p0/m, p0/m, z31.h, z0.h
+.*: 81bf0008 bfmopa za0.h, p0/m, p0/m, z0.h, z31.h
+.*: 81afad48 bfmopa za0.h, p3/m, p5/m, z10.h, z15.h
+.*: 81b965e9 bfmopa za1.h, p1/m, p3/m, z15.h, z25.h
+.*: 81a00018 bfmops za0.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a00019 bfmops za1.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a01c18 bfmops za0.h, p7/m, p0/m, z0.h, z0.h
+.*: 81a0e018 bfmops za0.h, p0/m, p7/m, z0.h, z0.h
+.*: 81a003f8 bfmops za0.h, p0/m, p0/m, z31.h, z0.h
+.*: 81bf0018 bfmops za0.h, p0/m, p0/m, z0.h, z31.h
+.*: 81afad58 bfmops za0.h, p3/m, p5/m, z10.h, z15.h
+.*: 81b965f9 bfmops za1.h, p1/m, p3/m, z15.h, z25.h
diff --git a/gas/testsuite/gas/aarch64/sme-b16b16-1.s b/gas/testsuite/gas/aarch64/sme-b16b16-1.s
new file mode 100644
index 00000000000..127cae4feb6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-b16b16-1.s
@@ -0,0 +1,143 @@
+/* BFADD. */
+bfadd za.h[w8, 0, vgx2], {z0.h - z1.h}
+bfadd za.h[w11, 0, vgx2], {z0.h - z1.h}
+bfadd za.h[w8, 7, vgx2], {z0.h - z1.h}
+bfadd za.h[w8, 0, vgx2], {z30.h - z31.h}
+bfadd za.h[w8, 3], {z30.h - z31.h}
+
+bfadd za.h[w8, 0, vgx4], {z0.h - z3.h}
+bfadd za.h[w11, 0, vgx4], {z0.h - z3.h}
+bfadd za.h[w8, 7, vgx4], {z0.h - z3.h}
+bfadd za.h[w8, 0, vgx4], {z28.h - z31.h}
+bfadd za.h[w8, 3], {z28.h - z31.h}
+
+/* BFSUB. */
+bfsub za.h[w8, 0, vgx2], {z0.h - z1.h}
+bfsub za.h[w11, 0, vgx2], {z0.h - z1.h}
+bfsub za.h[w8, 7, vgx2], {z0.h - z1.h}
+bfsub za.h[w8, 0, vgx2], {z30.h - z31.h}
+bfsub za.h[w8, 3], {z30.h - z31.h}
+
+bfsub za.h[w8, 0, vgx4], {z0.h - z3.h}
+bfsub za.h[w11, 0, vgx4], {z0.h - z3.h}
+bfsub za.h[w8, 7, vgx4], {z0.h - z3.h}
+bfsub za.h[w8, 0, vgx4], {z28.h - z31.h}
+bfsub za.h[w8, 3], {z28.h - z31.h}
+
+/* BFMLA (multiple and indexed vector). */
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[3]
+bfmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[3]
+bfmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* BFMLA (multiple and single vector). */
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+bfmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+bfmla za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+bfmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+bfmla za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* BFMLA (multiple vectors). */
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+bfmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+bfmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
+
+/* BFMLS (multiple and indexed vector). */
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[3]
+bfmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[3]
+bfmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* BFMLS (multiple and single vector). */
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+bfmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+bfmls za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+bfmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+bfmls za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* BFMLS (multiple vectors). */
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+bfmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+bfmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
+
+/* BFMOPA. */
+bfmopa ZA0.h, p0/m, p0/m, z0.h, z0.h
+bfmopa ZA1.h, p0/m, p0/m, z0.h, z0.h
+bfmopa ZA0.h, p7/m, p0/m, z0.h, z0.h
+bfmopa ZA0.h, p0/m, p7/m, z0.h, z0.h
+bfmopa ZA0.h, p0/m, p0/m, z31.h, z0.h
+bfmopa ZA0.h, p0/m, p0/m, z0.h, z31.h
+bfmopa ZA0.h, p3/m, p5/m, z10.h, z15.h
+bfmopa ZA1.h, p1/m, p3/m, z15.h, z25.h
+
+/* BFMOPS. */
+bfmops ZA0.h, p0/m, p0/m, z0.h, z0.h
+bfmops ZA1.h, p0/m, p0/m, z0.h, z0.h
+bfmops ZA0.h, p7/m, p0/m, z0.h, z0.h
+bfmops ZA0.h, p0/m, p7/m, z0.h, z0.h
+bfmops ZA0.h, p0/m, p0/m, z31.h, z0.h
+bfmops ZA0.h, p0/m, p0/m, z0.h, z31.h
+bfmops ZA0.h, p3/m, p5/m, z10.h, z15.h
+bfmops ZA1.h, p1/m, p3/m, z15.h, z25.h
diff --git a/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.d b/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.d
new file mode 100644
index 00000000000..c365b6b3513
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.d
@@ -0,0 +1,3 @@
+#name: Test of invalid SME2 non-widening BFloat16 instructions.
+#as: -march=armv8-a+sme-b16b16
+#error_output: sme-b16b16-bad-1.l
diff --git a/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.l b/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.l
new file mode 100644
index 00000000000..8bb637669ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.l
@@ -0,0 +1,193 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `bfadd za.s\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfadd za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w13,0,vgx2\],{ ?z1.h-z0.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfadd za.h\[w8,11,vgx3\],{ ?z0.h-z1.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w8,0,vgx2\],{ ?z0.h-z4.h ?}'
+.*: Error: operand mismatch -- `bfadd za.s\[w8,0,vgx4\],{ ?z0.h-z3.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfadd za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w14,0,vgx4\],{ ?z10.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfadd za.h\[w8,15,vgx1\],{ ?z3.h-z2.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfadd za.h\[w8,0,vgx4\],{ ?z30.h-z31.h ?}'
+.*: Error: operand mismatch -- `bfsub za.s\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfsub za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w13,0,vgx2\],{ ?z1.h-z0.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfsub za.h\[w8,11,vgx3\],{ ?z0.h-z1.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w8,0,vgx2\],{ ?z0.h-z4.h ?}'
+.*: Error: operand mismatch -- `bfsub za.s\[w8,0,vgx4\],{ ?z0.h-z3.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfsub za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w14,0,vgx4\],{ ?z10.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfsub za.h\[w8,15,vgx1\],{ ?z3.h-z2.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfsub za.h\[w8,0,vgx4\],{ ?z30.h-z31.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,0,vgx3\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,0,vgx3\],{ ?z31.h-z0.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z31.h-z2.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,15,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 3 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmla za.b\[w8,20,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 20, vgx2\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,15,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmla za.b\[w8,20,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 20, vgx4\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,0,vgx3\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,0,vgx3\],{ ?z31.h-z0.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z31.h-z2.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,15,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 3 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmls za.b\[w8,20,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 20, vgx2\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,15,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmls za.b\[w8,20,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 20, vgx4\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: operand mismatch -- `bfmopa ZA1.h,p0,p0/m,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za1.h, p0/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmopa ZA0.h,p7/m,p0,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za0.h, p7/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmopa ZA0.h,p0/m,p7/m,z0.s,z0.s'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za0.h, p0/m, p7/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmopa ZA0.h,p0/m,p0/m,z31.d,z0.d'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za0.h, p0/m, p0/m, z31.h, z0.h
+.*: Error: ZA tile number out of range at operand 1 -- `bfmopa ZA2.h,p0/m,p8/m,z0.s,z31.b'
+.*: Error: ZA tile number out of range at operand 1 -- `bfmopa ZA4.h,p15/m,p11/m,z0.s,z31.b'
+.*: Error: operand mismatch -- `bfmops ZA1.h,p0,p0/m,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmops za1.h, p0/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmops ZA0.h,p7/m,p0,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmops za0.h, p7/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmops ZA0.h,p0/m,p7/m,z0.s,z0.s'
+.*: Info: did you mean this\?
+.*: Info: bfmops za0.h, p0/m, p7/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmops ZA0.h,p0/m,p0/m,z31.d,z0.d'
+.*: Info: did you mean this\?
+.*: Info: bfmops za0.h, p0/m, p0/m, z31.h, z0.h
+.*: Error: ZA tile number out of range at operand 1 -- `bfmops ZA2.h,p0/m,p8/m,z0.s,z31.b'
+.*: Error: ZA tile number out of range at operand 1 -- `bfmops ZA4.h,p15/m,p11/m,z0.s,z31.b'
diff --git a/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.s b/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.s
new file mode 100644
index 00000000000..1ba22e18e3c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-b16b16-bad-1.s
@@ -0,0 +1,173 @@
+/* BFADD. */
+bfadd za.s[w8, 0, vgx2], {z0.h - z1.h}
+bfadd za.h[w13, 0, vgx2], {z1.h - z0.h}
+bfadd za.h[w8, 11, vgx3], {z0.h - z1.h}
+bfadd za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+bfadd za.s[w8, 0, vgx4], {z0.h - z3.h}
+bfadd za.h[w14, 0, vgx4], {z10.h - z3.h}
+bfadd za.h[w8, 15, vgx1], {z3.h - z2.h}
+bfadd za.h[w8, 0, vgx4], {z30.h - z31.h}
+
+/* BFSUB. */
+bfsub za.s[w8, 0, vgx2], {z0.h - z1.h}
+bfsub za.h[w13, 0, vgx2], {z1.h - z0.h}
+bfsub za.h[w8, 11, vgx3], {z0.h - z1.h}
+bfsub za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+bfsub za.s[w8, 0, vgx4], {z0.h - z3.h}
+bfsub za.h[w14, 0, vgx4], {z10.h - z3.h}
+bfsub za.h[w8, 15, vgx1], {z3.h - z2.h}
+bfsub za.h[w8, 0, vgx4], {z30.h - z31.h}
+
+/* BFMLA (multiple and indexed vector). */
+bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmla za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0.h}, z0.h
+bfmla za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0 - z1}
+
+bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+bfmla za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0.h}, z0.h
+bfmla za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0 - z1}
+
+/* BFMLA (multiple and single vector). */
+bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+bfmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+bfmla za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+bfmla za.h[w8, 0, vgx2], {z0.h}, z15.h
+bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+bfmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+bfmla za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+bfmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+bfmla za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+bfmla za.h[w8, 0, vgx4], {z0.h}, z15.h
+bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* BFMLA (multiple vectors). */
+bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+bfmla za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+bfmla za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmla za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+bfmla za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmla za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+bfmla za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmla za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmla za.b[w8, 20, vgx4], {z0.h}, {z30.h}
+
+/* BFMLS (multiple and indexed vector). */
+bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmls za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0.h}, z0.h
+bfmls za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0 - z1}
+
+bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+bfmls za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0.h}, z0.h
+bfmls za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0 - z1}
+
+/* BFMLS (multiple and single vector). */
+bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+bfmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+bfmls za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+bfmls za.h[w8, 0, vgx2], {z0.h}, z15.h
+bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+bfmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+bfmls za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+bfmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+bfmls za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+bfmls za.h[w8, 0, vgx4], {z0.h}, z15.h
+bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* BFMLS (multiple vectors). */
+bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+bfmls za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+bfmls za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmls za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+bfmls za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmls za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+bfmls za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmls za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmls za.b[w8, 20, vgx4], {z0.h}, {z30.h}
+
+/* BFMOPA. */
+bfmopa ZA0.s, p0/m, p0/m, z0.h, z0.h
+bfmopa ZA1.h, p0, p0/m, z0.h, z0.h
+bfmopa ZA0.h, p7/m, p0, z0.h, z0.h
+bfmopa ZA0.h, p0/m, p7/m, z0.s, z0.s
+bfmopa ZA0.h, p0/m, p0/m, z31.d, z0.d
+bfmopa ZA2.h, p0/m, p8/m, z0.s, z31.b
+bfmopa ZA4.h, p15/m, p11/m, z0.s, z31.b
+
+/* BFMOPS. */
+bfmops ZA0.s, p0/m, p0/m, z0.h, z0.h
+bfmops ZA1.h, p0, p0/m, z0.h, z0.h
+bfmops ZA0.h, p7/m, p0, z0.h, z0.h
+bfmops ZA0.h, p0/m, p7/m, z0.s, z0.s
+bfmops ZA0.h, p0/m, p0/m, z31.d, z0.d
+bfmops ZA2.h, p0/m, p8/m, z0.s, z31.b
+bfmops ZA4.h, p15/m, p11/m, z0.s, z31.b
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c438382a0fa..755373557fc 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -266,6 +266,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_F16F16,
/* SVE Z-targeting non-widening BFloat16 instructions. */
AARCH64_FEATURE_SVE_B16B16,
+ /* SME non-widening BFloat16 instructions. */
+ AARCH64_FEATURE_SME_B16B16,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index f9cf325d013..07e12f6d252 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3330;
+ return 3348;
}
else
{
@@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3332;
+ return 3350;
}
}
else
@@ -235,7 +235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3331;
+ return 3349;
}
else
{
@@ -243,7 +243,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3333;
+ return 3351;
}
}
}
@@ -253,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x0011xxxxxx1xxxxxxxxx
movaz. */
- return 3334;
+ return 3352;
}
}
}
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3462;
+ return 3480;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3463;
+ return 3481;
}
else
{
@@ -318,7 +318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x10xxxxxxxxxxxxxx
luti4. */
- return 3327;
+ return 3345;
}
}
else
@@ -327,7 +327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xx1xxxxxxxxxxxxxx
luti4. */
- return 3326;
+ return 3344;
}
}
}
@@ -369,7 +369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x011xxxxx001xxxxxxxxx
movaz. */
- return 3320;
+ return 3338;
}
else
{
@@ -377,7 +377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x011xxxxx001xxxxxxxxx
movaz. */
- return 3322;
+ return 3340;
}
}
else
@@ -388,7 +388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x011xxxxx001xxxxxxxxx
movaz. */
- return 3321;
+ return 3339;
}
else
{
@@ -396,7 +396,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x011xxxxx001xxxxxxxxx
movaz. */
- return 3323;
+ return 3341;
}
}
}
@@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011000xxx00xxxxxxxxxx
zero. */
- return 3335;
+ return 3353;
}
else
{
@@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011100xxx00xxxxxxxxxx
zero. */
- return 3336;
+ return 3354;
}
}
else
@@ -439,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011010xxx00xxxxxxxxxx
zero. */
- return 3338;
+ return 3356;
}
else
{
@@ -447,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011110xxx00xxxxxxxxxx
zero. */
- return 3341;
+ return 3359;
}
}
}
@@ -461,7 +461,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011001xxx00xxxxxxxxxx
zero. */
- return 3337;
+ return 3355;
}
else
{
@@ -469,7 +469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011101xxx00xxxxxxxxxx
zero. */
- return 3340;
+ return 3358;
}
}
else
@@ -480,7 +480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011011xxx00xxxxxxxxxx
zero. */
- return 3339;
+ return 3357;
}
else
{
@@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011111xxx00xxxxxxxxxx
zero. */
- return 3342;
+ return 3360;
}
}
}
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3464;
+ return 3482;
}
}
else
@@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx0xx00xxxxxxxxxx
luti2. */
- return 3325;
+ return 3343;
}
else
{
@@ -571,7 +571,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx1xx00xxxxxxxxxx
luti2. */
- return 3324;
+ return 3342;
}
}
}
@@ -602,7 +602,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx101xxxxxxxxx
movaz. */
- return 3328;
+ return 3346;
}
}
}
@@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000xx11xxxxx011xxxxxxxxx
movaz. */
- return 3316;
+ return 3334;
}
else
{
@@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100xx11xxxxx011xxxxxxxxx
movaz. */
- return 3318;
+ return 3336;
}
}
else
@@ -658,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010xx11xxxxx011xxxxxxxxx
movaz. */
- return 3317;
+ return 3335;
}
else
{
@@ -666,7 +666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110xx11xxxxx011xxxxxxxxx
movaz. */
- return 3319;
+ return 3337;
}
}
}
@@ -698,7 +698,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx111xxxxxxxxx
movaz. */
- return 3329;
+ return 3347;
}
}
}
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3530;
+ return 3548;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3529;
+ return 3547;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3523;
+ return 3541;
}
}
}
@@ -1754,7 +1754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx00xxxx
fmla. */
- return 3345;
+ return 3363;
}
else
{
@@ -1764,7 +1764,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx000xxxx
fmla. */
- return 3346;
+ return 3364;
}
else
{
@@ -1772,28 +1772,50 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx100xxxx
fdot. */
- return 3508;
+ return 3526;
}
}
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx10xxxx
- usmlall. */
- return 2933;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx10xxxx
+ usmlall. */
+ return 2933;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx10xxxx
+ usmlall. */
+ return 2934;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx10xxxx
- usmlall. */
- return 2934;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx10xxxx
+ bfmla. */
+ return 3320;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxxx10xxxx
+ bfmla. */
+ return 3321;
+ }
}
}
}
@@ -1883,7 +1905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx01xxxx
fmls. */
- return 3351;
+ return 3369;
}
else
{
@@ -1891,27 +1913,49 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxxx01xxxx
fmls. */
- return 3352;
+ return 3370;
}
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx11xxxx
- sumlall. */
- return 2849;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx11xxxx
+ sumlall. */
+ return 2849;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx11xxxx
+ sumlall. */
+ return 2850;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx11xxxx
- sumlall. */
- return 2850;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx11xxxx
+ bfmls. */
+ return 3326;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxxx11xxxx
+ bfmls. */
+ return 3327;
+ }
}
}
}
@@ -2135,7 +2179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3343;
+ return 3361;
}
}
else
@@ -2179,7 +2223,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3522;
+ return 3540;
}
}
}
@@ -2284,7 +2328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3515;
+ return 3533;
}
}
}
@@ -2330,7 +2374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx11xxx
fmops. */
- return 3344;
+ return 3362;
}
}
else
@@ -2468,7 +2512,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3514;
+ return 3532;
}
}
}
@@ -2510,7 +2554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3521;
+ return 3539;
}
else
{
@@ -2878,7 +2922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3501;
+ return 3519;
}
else
{
@@ -2947,7 +2991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3502;
+ return 3520;
}
else
{
@@ -3026,7 +3070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3513;
+ return 3531;
}
else
{
@@ -3081,7 +3125,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3532;
+ return 3550;
}
else
{
@@ -3099,7 +3143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3507;
+ return 3525;
}
}
}
@@ -3173,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3531;
+ return 3549;
}
}
}
@@ -3253,7 +3297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3533;
+ return 3551;
}
else
{
@@ -3347,21 +3391,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001xx1xxxxxxxxxxxxxxxx0xxxx
- fmopa. */
- return 2415;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx00xxx
+ fmopa. */
+ return 2415;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx10xxx
+ fmops. */
+ return 2418;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001xx1xxxxxxxxxxxxxxxx1xxxx
- fmops. */
- return 2418;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx01xxx
+ bfmopa. */
+ return 3332;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx11xxx
+ bfmops. */
+ return 3333;
+ }
}
}
else
@@ -3430,7 +3496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3527;
+ return 3545;
}
else
{
@@ -3438,7 +3504,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3528;
+ return 3546;
}
}
}
@@ -3493,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3525;
+ return 3543;
}
else
{
@@ -3501,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3526;
+ return 3544;
}
}
}
@@ -3555,7 +3621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3511;
+ return 3529;
}
else
{
@@ -3563,7 +3629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3512;
+ return 3530;
}
}
}
@@ -3625,7 +3691,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3519;
+ return 3537;
}
else
{
@@ -3633,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3520;
+ return 3538;
}
}
}
@@ -3688,7 +3754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3517;
+ return 3535;
}
else
{
@@ -3696,7 +3762,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3518;
+ return 3536;
}
}
}
@@ -3765,7 +3831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3524;
+ return 3542;
}
}
else
@@ -3848,7 +3914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3516;
+ return 3534;
}
}
else
@@ -3857,11 +3923,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx111xxxxx00xxx
- fmla. */
- return 3347;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3365;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010110xxxx0xx111xxxxx00xxx
+ bfmla. */
+ return 3322;
+ }
}
else
{
@@ -3877,11 +3954,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x10x1x00xx111xxxxx00xxx
- fadd. */
- return 3465;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x1x00xx111xxxxx00xxx
+ fadd. */
+ return 3483;
+ [...]
[diff truncated at 100000 bytes]
More information about the Binutils-cvs
mailing list