[binutils-gdb] aarch64: Add support for FEAT_SVE_B16B16 min and max instructions.
SRINATH PARVATHANENI
sripar01@sourceware.org
Fri Jan 10 16:48:18 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=150bfae1d719a3b5c12edc780f0b360a1056b802
commit 150bfae1d719a3b5c12edc780f0b360a1056b802
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Fri Jan 10 16:47:31 2025 +0000
aarch64: Add support for FEAT_SVE_B16B16 min and max instructions.
This patch adds support for SME Z-targeting multi-vector non-widening
BFloat16 instructions, under tick FEAT_SVE_B16B16 and command line flag
"+sve-b16b16+sme2".
Also the test files related to FEAT_SVE_B16B16 (+sme2) are prefixed with
sve-b16b16-sme2*.
eg: sve-b16b16-sme2-1.s, sve-b16b16-sme2-1.d.
The spec for this feature and instructions is availabe here [1]:
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
Diff:
---
gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d | 3 +
gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.l | 159 ++++++++
gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.s | 136 +++++++
gas/testsuite/gas/aarch64/sve-b16b16-sme2.d | 122 ++++++
gas/testsuite/gas/aarch64/sve-b16b16-sme2.s | 138 +++++++
gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l | 4 +-
opcodes/aarch64-dis-2.c | 472 ++++++++++++----------
opcodes/aarch64-tbl.h | 29 ++
8 files changed, 843 insertions(+), 220 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d
new file mode 100644
index 00000000000..24ebb088409
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d
@@ -0,0 +1,3 @@
+#name: Test of invalid SME2 non-widening BFloat16 min max instructions.
+#as: -march=armv8-a+sve-b16b16+sme2
+#error_output: sve-b16b16-sme2-bad-1.l
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.l b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.l
new file mode 100644
index 00000000000..5fd29f90077
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.l
@@ -0,0 +1,159 @@
+.*: Assembler messages:
+.*: Error: too many registers in vector register list at operand 2 -- `bfmax { ?z30.h-z31.h ?},{ ?z0.h-z31.h ?},z0.h'
+.*: Error: z0-z15 expected at operand 3 -- `bfmax { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},z16.h'
+.*: Error: operand mismatch -- `bfmax { ?z14.s-z15.s ?},{ ?z14.s-z15.s ?},z1.h'
+.*: Info: did you mean this\?
+.*: Info: bfmax { ?z14.h-z15.h ?}, { ?z14.h-z15.h ?}, z1.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z2.h-z7.h ?},{ ?z30.h-z7.h ?},z3.d'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z4.h-z3.h ?},{ ?z4.h-z3.h ?},z7.b'
+.*: Error: operand mismatch -- `bfmax { ?z28.h-z31.h ?},{ ?z28.s-z31.h ?},z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmax { ?z28.h-z31.h ?}, { ?z28.h-z31.h ?}, z0.h
+.*: Error: z0-z15 expected at operand 3 -- `bfmax { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},z16.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z10.h-z15.h ?},{ ?z10.h-z15.h ?},z1.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z14.h-z7.h ?},{ ?z4.h-z7.h ?},z3.s'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z4.h-z17.h ?},{ ?z1.h-z7.h ?},z17.b'
+.*: Error: operand mismatch -- `bfmax { ?z0.s-z1.h ?},{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmax { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: Error: invalid range in vector register list at operand 2 -- `bfmax { ?z30.h-z31.h ?},{ ?z31.s-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: operand mismatch -- `bfmax { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},{ ?z30.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmax { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfmax { ?z14.h-z15.h ?},{ ?z14.h-z15.h ?},{ ?z14.s-z10.s ?}'
+.*: Error: operand 2 must be the same register as operand 1 -- `bfmax { ?z6.h-z7.h ?},{ ?z16.h-z17.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: comma expected between operands at operand 3 -- `bfmax { ?z2.h-z3.h ?},{ ?z2.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z20.h-z31.h ?},{ ?z0.h-z3.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfmax { ?z28.h-z31.h ?},{ ?z21.s-z31.s ?},{ ?z0.h-z3.h ?}'
+.*: Error: operand mismatch -- `bfmax { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},{ ?z28.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmax { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfmax { ?z12.h-z15.h ?},{ ?z12.h-z15.h ?},{ ?z10.h-z25.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z4.h-z17.h ?},{ ?z4.h-z7.h ?},{ ?z14.h-z17.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmax { ?z14.h-z7.h ?},{ ?z4.s-z7.b ?},{ ?z10.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfmaxnm { ?z30.h-z31.h ?},{ ?z0.h-z31.h ?},z0.h'
+.*: Error: z0-z15 expected at operand 3 -- `bfmaxnm { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},z16.h'
+.*: Error: operand mismatch -- `bfmaxnm { ?z14.s-z15.s ?},{ ?z14.s-z15.s ?},z1.h'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm { ?z14.h-z15.h ?}, { ?z14.h-z15.h ?}, z1.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z2.h-z7.h ?},{ ?z30.h-z7.h ?},z3.d'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z4.h-z3.h ?},{ ?z4.h-z3.h ?},z7.b'
+.*: Error: operand mismatch -- `bfmaxnm { ?z28.h-z31.h ?},{ ?z28.s-z31.h ?},z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm { ?z28.h-z31.h ?}, { ?z28.h-z31.h ?}, z0.h
+.*: Error: z0-z15 expected at operand 3 -- `bfmaxnm { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},z16.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z10.h-z15.h ?},{ ?z10.h-z15.h ?},z1.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z14.h-z7.h ?},{ ?z4.h-z7.h ?},z3.s'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z4.h-z17.h ?},{ ?z1.h-z7.h ?},z17.b'
+.*: Error: operand mismatch -- `bfmaxnm { ?z0.s-z1.h ?},{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: Error: invalid range in vector register list at operand 2 -- `bfmaxnm { ?z30.h-z31.h ?},{ ?z31.s-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: operand mismatch -- `bfmaxnm { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},{ ?z30.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfmaxnm { ?z14.h-z15.h ?},{ ?z14.h-z15.h ?},{ ?z14.s-z10.s ?}'
+.*: Error: operand 2 must be the same register as operand 1 -- `bfmaxnm { ?z6.h-z7.h ?},{ ?z16.h-z17.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: comma expected between operands at operand 3 -- `bfmaxnm { ?z2.h-z3.h ?},{ ?z2.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z20.h-z31.h ?},{ ?z0.h-z3.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfmaxnm { ?z28.h-z31.h ?},{ ?z21.s-z31.s ?},{ ?z0.h-z3.h ?}'
+.*: Error: operand mismatch -- `bfmaxnm { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},{ ?z28.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfmaxnm { ?z12.h-z15.h ?},{ ?z12.h-z15.h ?},{ ?z10.h-z25.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z4.h-z17.h ?},{ ?z4.h-z7.h ?},{ ?z14.h-z17.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm { ?z14.h-z7.h ?},{ ?z4.s-z7.b ?},{ ?z10.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfmin { ?z30.h-z31.h ?},{ ?z0.h-z31.h ?},z0.h'
+.*: Error: z0-z15 expected at operand 3 -- `bfmin { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},z16.h'
+.*: Error: operand mismatch -- `bfmin { ?z14.s-z15.s ?},{ ?z14.s-z15.s ?},z1.h'
+.*: Info: did you mean this\?
+.*: Info: bfmin { ?z14.h-z15.h ?}, { ?z14.h-z15.h ?}, z1.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z2.h-z7.h ?},{ ?z30.h-z7.h ?},z3.d'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z4.h-z3.h ?},{ ?z4.h-z3.h ?},z7.b'
+.*: Error: operand mismatch -- `bfmin { ?z28.h-z31.h ?},{ ?z28.s-z31.h ?},z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmin { ?z28.h-z31.h ?}, { ?z28.h-z31.h ?}, z0.h
+.*: Error: z0-z15 expected at operand 3 -- `bfmin { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},z16.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z10.h-z15.h ?},{ ?z10.h-z15.h ?},z1.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z14.h-z7.h ?},{ ?z4.h-z7.h ?},z3.s'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z4.h-z17.h ?},{ ?z1.h-z7.h ?},z17.b'
+.*: Error: operand mismatch -- `bfmin { ?z0.s-z1.h ?},{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmin { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: Error: invalid range in vector register list at operand 2 -- `bfmin { ?z30.h-z31.h ?},{ ?z31.s-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: operand mismatch -- `bfmin { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},{ ?z30.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmin { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfmin { ?z14.h-z15.h ?},{ ?z14.h-z15.h ?},{ ?z14.s-z10.s ?}'
+.*: Error: operand 2 must be the same register as operand 1 -- `bfmin { ?z6.h-z7.h ?},{ ?z16.h-z17.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: comma expected between operands at operand 3 -- `bfmin { ?z2.h-z3.h ?},{ ?z2.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z20.h-z31.h ?},{ ?z0.h-z3.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfmin { ?z28.h-z31.h ?},{ ?z21.s-z31.s ?},{ ?z0.h-z3.h ?}'
+.*: Error: operand mismatch -- `bfmin { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},{ ?z28.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmin { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfmin { ?z12.h-z15.h ?},{ ?z12.h-z15.h ?},{ ?z10.h-z25.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z4.h-z17.h ?},{ ?z4.h-z7.h ?},{ ?z14.h-z17.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfmin { ?z14.h-z7.h ?},{ ?z4.s-z7.b ?},{ ?z10.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfminnm { ?z30.h-z31.h ?},{ ?z0.h-z31.h ?},z0.h'
+.*: Error: z0-z15 expected at operand 3 -- `bfminnm { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},z16.h'
+.*: Error: operand mismatch -- `bfminnm { ?z14.s-z15.s ?},{ ?z14.s-z15.s ?},z1.h'
+.*: Info: did you mean this\?
+.*: Info: bfminnm { ?z14.h-z15.h ?}, { ?z14.h-z15.h ?}, z1.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z2.h-z7.h ?},{ ?z30.h-z7.h ?},z3.d'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z4.h-z3.h ?},{ ?z4.h-z3.h ?},z7.b'
+.*: Error: operand mismatch -- `bfminnm { ?z28.h-z31.h ?},{ ?z28.s-z31.h ?},z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfminnm { ?z28.h-z31.h ?}, { ?z28.h-z31.h ?}, z0.h
+.*: Error: z0-z15 expected at operand 3 -- `bfminnm { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},z16.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z10.h-z15.h ?},{ ?z10.h-z15.h ?},z1.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z14.h-z7.h ?},{ ?z4.h-z7.h ?},z3.s'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z4.h-z17.h ?},{ ?z1.h-z7.h ?},z17.b'
+.*: Error: operand mismatch -- `bfminnm { ?z0.s-z1.h ?},{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfminnm { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: Error: invalid range in vector register list at operand 2 -- `bfminnm { ?z30.h-z31.h ?},{ ?z31.s-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: operand mismatch -- `bfminnm { ?z0.h-z1.h ?},{ ?z0.h-z1.h ?},{ ?z30.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfminnm { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfminnm { ?z14.h-z15.h ?},{ ?z14.h-z15.h ?},{ ?z14.s-z10.s ?}'
+.*: Error: operand 2 must be the same register as operand 1 -- `bfminnm { ?z6.h-z7.h ?},{ ?z16.h-z17.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: comma expected between operands at operand 3 -- `bfminnm { ?z2.h-z3.h ?},{ ?z2.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z20.h-z31.h ?},{ ?z0.h-z3.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfminnm { ?z28.h-z31.h ?},{ ?z21.s-z31.s ?},{ ?z0.h-z3.h ?}'
+.*: Error: operand mismatch -- `bfminnm { ?z0.h-z3.h ?},{ ?z0.h-z3.h ?},{ ?z28.b-z31.b ?}'
+.*: Info: did you mean this\?
+.*: Info: bfminnm { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: Error: too many registers in vector register list at operand 3 -- `bfminnm { ?z12.h-z15.h ?},{ ?z12.h-z15.h ?},{ ?z10.h-z25.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z4.h-z17.h ?},{ ?z4.h-z7.h ?},{ ?z14.h-z17.h ?}'
+.*: Error: too many registers in vector register list at operand 1 -- `bfminnm { ?z14.h-z7.h ?},{ ?z4.s-z7.b ?},{ ?z10.h-z3.h ?}'
+.*: Error: operand mismatch -- `bfclamp { ?z0.s-z1.s ?},z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z0.h-z1.h ?}, z0.h, z0.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfclamp { ?z31.h-z30.h ?},z0.h,z0.h'
+.*: Error: operand mismatch -- `bfclamp { ?z0.h-z1.h ?},z31.s,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z0.h-z1.h ?}, z31.h, z0.h
+.*: Error: operand mismatch -- `bfclamp { ?z0.h-z1.h ?},z0.h,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z0.h-z1.h ?}, z0.h, z31.h
+.*: Error: operand mismatch -- `bfclamp { ?z16.h-z17.h ?},z1.b,z15.b'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z16.h-z17.h ?}, z1.h, z15.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfclamp { ?z16.h-z21.h ?},z3.s,z7.d'
+.*: Error: invalid range in vector register list at operand 1 -- `bfclamp { ?z2.h-z2.h ?},z7.s,z31.d'
+.*: Error: operand mismatch -- `bfclamp { ?z0.s-z3.s ?},z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z0.h-z3.h ?}, z0.h, z0.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfclamp { ?z25.h-z31.h ?},z0.h,z0.h'
+.*: Error: operand mismatch -- `bfclamp { ?z0.h-z3.h ?},z31.s,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z0.h-z3.h ?}, z31.h, z0.h
+.*: Error: operand mismatch -- `bfclamp { ?z0.h-z3.h ?},z0.h,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z0.h-z3.h ?}, z0.h, z31.h
+.*: Error: operand mismatch -- `bfclamp { ?z31.h-z2.h ?},z1.b,z15.b'
+.*: Info: did you mean this\?
+.*: Info: bfclamp { ?z31.h-z2.h ?}, z1.h, z15.h
+.*: Error: too many registers in vector register list at operand 1 -- `bfclamp { ?z18.s-z15.s ?},z3.h,z7.h'
+.*: Error: too many registers in vector register list at operand 1 -- `bfclamp { ?z14.h-z27.h ?},z7.s,z31.d'
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.s b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.s
new file mode 100644
index 00000000000..fb27f2d078c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.s
@@ -0,0 +1,136 @@
+/* BFMAX. */
+bfmax {z0.h - z1.s}, {z0.h - z1.h}, z0.h
+bfmax {z30.h - z31.h}, {z0.h - z31.h}, z0.h
+bfmax {z0.h - z1.h}, {z0.h - z1.h}, z16.h
+bfmax {z14.s - z15.s}, {z14.s - z15.s}, z1.h
+bfmax {z2.h - z7.h}, {z30.h - z7.h}, z3.d
+bfmax {z4.h - z3.h}, {z4.h - z3.h}, z7.b
+
+bfmax {z0.h - z3.s}, {z0.h - z3.h}, z0.h
+bfmax {z28.h - z31.h}, {z28.s - z31.h}, z0.h
+bfmax {z0.h - z3.h}, {z0.h - z3.h}, z16.h
+bfmax {z10.h - z15.h}, {z10.h - z15.h}, z1.h
+bfmax {z14.h - z7.h}, {z4.h - z7.h}, z3.s
+bfmax {z4.h - z17.h}, {z1.h - z7.h}, z17.b
+
+/* BFMAX (multiple vectors). */
+bfmax {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfmax {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h}
+bfmax {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b}
+bfmax {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s}
+bfmax {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h}
+bfmax {z2.h - z3.h}, {z2.h - z3.h}
+
+bfmax {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfmax {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h}
+bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b}
+bfmax {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h}
+bfmax {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h}
+bfmax {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h}
+
+/* BFMAXNM. */
+bfmaxnm {z0.h - z1.s}, {z0.h - z1.h}, z0.h
+bfmaxnm {z30.h - z31.h}, {z0.h - z31.h}, z0.h
+bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, z16.h
+bfmaxnm {z14.s - z15.s}, {z14.s - z15.s}, z1.h
+bfmaxnm {z2.h - z7.h}, {z30.h - z7.h}, z3.d
+bfmaxnm {z4.h - z3.h}, {z4.h - z3.h}, z7.b
+
+bfmaxnm {z0.h - z3.s}, {z0.h - z3.h}, z0.h
+bfmaxnm {z28.h - z31.h}, {z28.s - z31.h}, z0.h
+bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z16.h
+bfmaxnm {z10.h - z15.h}, {z10.h - z15.h}, z1.h
+bfmaxnm {z14.h - z7.h}, {z4.h - z7.h}, z3.s
+bfmaxnm {z4.h - z17.h}, {z1.h - z7.h}, z17.b
+
+/* BFMAXNM (multiple vectors). */
+bfmaxnm {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfmaxnm {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h}
+bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b}
+bfmaxnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s}
+bfmaxnm {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h}
+bfmaxnm {z2.h - z3.h}, {z2.h - z3.h}
+
+bfmaxnm {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfmaxnm {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h}
+bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b}
+bfmaxnm {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h}
+bfmaxnm {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h}
+bfmaxnm {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h}
+
+/* BFMIN. */
+bfmin {z0.h - z1.s}, {z0.h - z1.h}, z0.h
+bfmin {z30.h - z31.h}, {z0.h - z31.h}, z0.h
+bfmin {z0.h - z1.h}, {z0.h - z1.h}, z16.h
+bfmin {z14.s - z15.s}, {z14.s - z15.s}, z1.h
+bfmin {z2.h - z7.h}, {z30.h - z7.h}, z3.d
+bfmin {z4.h - z3.h}, {z4.h - z3.h}, z7.b
+
+bfmin {z0.h - z3.s}, {z0.h - z3.h}, z0.h
+bfmin {z28.h - z31.h}, {z28.s - z31.h}, z0.h
+bfmin {z0.h - z3.h}, {z0.h - z3.h}, z16.h
+bfmin {z10.h - z15.h}, {z10.h - z15.h}, z1.h
+bfmin {z14.h - z7.h}, {z4.h - z7.h}, z3.s
+bfmin {z4.h - z17.h}, {z1.h - z7.h}, z17.b
+
+/* BFMIN (multiple vectors). */
+bfmin {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfmin {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h}
+bfmin {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b}
+bfmin {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s}
+bfmin {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h}
+bfmin {z2.h - z3.h}, {z2.h - z3.h}
+
+bfmin {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfmin {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h}
+bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b}
+bfmin {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h}
+bfmin {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h}
+bfmin {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h}
+
+/* BFMINNM. */
+bfminnm {z0.h - z1.s}, {z0.h - z1.h}, z0.h
+bfminnm {z30.h - z31.h}, {z0.h - z31.h}, z0.h
+bfminnm {z0.h - z1.h}, {z0.h - z1.h}, z16.h
+bfminnm {z14.s - z15.s}, {z14.s - z15.s}, z1.h
+bfminnm {z2.h - z7.h}, {z30.h - z7.h}, z3.d
+bfminnm {z4.h - z3.h}, {z4.h - z3.h}, z7.b
+
+bfminnm {z0.h - z3.s}, {z0.h - z3.h}, z0.h
+bfminnm {z28.h - z31.h}, {z28.s - z31.h}, z0.h
+bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z16.h
+bfminnm {z10.h - z15.h}, {z10.h - z15.h}, z1.h
+bfminnm {z14.h - z7.h}, {z4.h - z7.h}, z3.s
+bfminnm {z4.h - z17.h}, {z1.h - z7.h}, z17.b
+
+/* BFMINNM (multiple vectors). */
+bfminnm {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfminnm {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h}
+bfminnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b}
+bfminnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s}
+bfminnm {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h}
+bfminnm {z2.h - z3.h}, {z2.h - z3.h}
+
+bfminnm {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfminnm {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h}
+bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b}
+bfminnm {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h}
+bfminnm {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h}
+bfminnm {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h}
+
+/* BFCLAMP. */
+bfclamp {z0.s - z1.s}, z0.h, z0.h
+bfclamp {z31.h - z30.h}, z0.h, z0.h
+bfclamp {z0.h - z1.h}, z31.s, z0.h
+bfclamp {z0.h - z1.h}, z0.h, z31.d
+bfclamp {z16.h - z17.h}, z1.b, z15.b
+bfclamp {z16.h - z21.h}, z3.s, z7.d
+bfclamp {z2.h - z2.h}, z7.s, z31.d
+
+bfclamp {z0.s - z3.s}, z0.h, z0.h
+bfclamp {z25.h - z31.h}, z0.h, z0.h
+bfclamp {z0.h - z3.h}, z31.s, z0.h
+bfclamp {z0.h - z3.h}, z0.h, z31.d
+bfclamp {z31.h - z2.h}, z1.b, z15.b
+bfclamp {z18.s - z15.s}, z3.h, z7.h
+bfclamp {z14.h - z27.h}, z7.s, z31.d
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2.d b/gas/testsuite/gas/aarch64/sve-b16b16-sme2.d
new file mode 100644
index 00000000000..b35bbf89e9b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2.d
@@ -0,0 +1,122 @@
+#name: Test of SME2 non-widening BFloat16 min max instructions.
+#as: -march=armv8-a+sve-b16b16+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c120a100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+.*: c120a11e bfmax {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+.*: c12fa100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+.*: c121a10e bfmax {z14.h-z15.h}, {z14.h-z15.h}, z1.h
+.*: c123a106 bfmax {z6.h-z7.h}, {z6.h-z7.h}, z3.h
+.*: c127a102 bfmax {z2.h-z3.h}, {z2.h-z3.h}, z7.h
+.*: c120a900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+.*: c120a91c bfmax {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+.*: c12fa900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+.*: c121a90c bfmax {z12.h-z15.h}, {z12.h-z15.h}, z1.h
+.*: c123a904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, z3.h
+.*: c127a904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, z7.h
+.*: c120b100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+.*: c120b11e bfmax {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+.*: c13eb100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+.*: c12eb10e bfmax {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h}
+.*: c126b106 bfmax {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h}
+.*: c122b102 bfmax {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h}
+.*: c120b900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+.*: c120b91c bfmax {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+.*: c13cb900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+.*: c12cb90c bfmax {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h}
+.*: c124b904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h}
+.*: c120b904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h}
+.*: c120a120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+.*: c120a13e bfmaxnm {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+.*: c12fa120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+.*: c121a12e bfmaxnm {z14.h-z15.h}, {z14.h-z15.h}, z1.h
+.*: c123a126 bfmaxnm {z6.h-z7.h}, {z6.h-z7.h}, z3.h
+.*: c127a122 bfmaxnm {z2.h-z3.h}, {z2.h-z3.h}, z7.h
+.*: c120a920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+.*: c120a93c bfmaxnm {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+.*: c12fa920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+.*: c121a92c bfmaxnm {z12.h-z15.h}, {z12.h-z15.h}, z1.h
+.*: c123a924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, z3.h
+.*: c127a924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, z7.h
+.*: c120b120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+.*: c120b13e bfmaxnm {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+.*: c13eb120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+.*: c12eb12e bfmaxnm {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h}
+.*: c126b126 bfmaxnm {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h}
+.*: c122b122 bfmaxnm {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h}
+.*: c120b920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+.*: c120b93c bfmaxnm {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+.*: c13cb920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+.*: c12cb92c bfmaxnm {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h}
+.*: c124b924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h}
+.*: c120b924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h}
+.*: c120a101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+.*: c120a11f bfmin {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+.*: c12fa101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+.*: c121a10f bfmin {z14.h-z15.h}, {z14.h-z15.h}, z1.h
+.*: c123a107 bfmin {z6.h-z7.h}, {z6.h-z7.h}, z3.h
+.*: c127a103 bfmin {z2.h-z3.h}, {z2.h-z3.h}, z7.h
+.*: c120a901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+.*: c120a91d bfmin {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+.*: c12fa901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+.*: c121a90d bfmin {z12.h-z15.h}, {z12.h-z15.h}, z1.h
+.*: c123a905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, z3.h
+.*: c127a905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, z7.h
+.*: c120b101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+.*: c120b11f bfmin {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+.*: c13eb101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+.*: c12eb10f bfmin {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h}
+.*: c126b107 bfmin {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h}
+.*: c122b103 bfmin {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h}
+.*: c120b901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+.*: c120b91d bfmin {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+.*: c13cb901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+.*: c12cb90d bfmin {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h}
+.*: c124b905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h}
+.*: c120b905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h}
+.*: c120a121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+.*: c120a13f bfminnm {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+.*: c12fa121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+.*: c121a12f bfminnm {z14.h-z15.h}, {z14.h-z15.h}, z1.h
+.*: c123a127 bfminnm {z6.h-z7.h}, {z6.h-z7.h}, z3.h
+.*: c127a123 bfminnm {z2.h-z3.h}, {z2.h-z3.h}, z7.h
+.*: c120a921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+.*: c120a93d bfminnm {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+.*: c12fa921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+.*: c121a92d bfminnm {z12.h-z15.h}, {z12.h-z15.h}, z1.h
+.*: c123a925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, z3.h
+.*: c127a925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, z7.h
+.*: c120b121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+.*: c120b13f bfminnm {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+.*: c13eb121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+.*: c12eb12f bfminnm {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h}
+.*: c126b127 bfminnm {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h}
+.*: c122b123 bfminnm {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h}
+.*: c120b921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+.*: c120b93d bfminnm {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+.*: c13cb921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+.*: c12cb92d bfminnm {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h}
+.*: c124b925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h}
+.*: c120b925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h}
+.*: c120c000 bfclamp {z0.h-z1.h}, z0.h, z0.h
+.*: c120c01e bfclamp {z30.h-z31.h}, z0.h, z0.h
+.*: c120c3e0 bfclamp {z0.h-z1.h}, z31.h, z0.h
+.*: c13fc000 bfclamp {z0.h-z1.h}, z0.h, z31.h
+.*: c12fc02e bfclamp {z14.h-z15.h}, z1.h, z15.h
+.*: c127c066 bfclamp {z6.h-z7.h}, z3.h, z7.h
+.*: c123c0e2 bfclamp {z2.h-z3.h}, z7.h, z3.h
+.*: c121c1f4 bfclamp {z20.h-z21.h}, z15.h, z1.h
+.*: c120c800 bfclamp {z0.h-z3.h}, z0.h, z0.h
+.*: c120c81c bfclamp {z28.h-z31.h}, z0.h, z0.h
+.*: c120cbe0 bfclamp {z0.h-z3.h}, z31.h, z0.h
+.*: c13fc800 bfclamp {z0.h-z3.h}, z0.h, z31.h
+.*: c12fc82c bfclamp {z12.h-z15.h}, z1.h, z15.h
+.*: c127c868 bfclamp {z8.h-z11.h}, z3.h, z7.h
+.*: c123c8e4 bfclamp {z4.h-z7.h}, z7.h, z3.h
+.*: c121c9f4 bfclamp {z20.h-z23.h}, z15.h, z1.h
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2.s b/gas/testsuite/gas/aarch64/sve-b16b16-sme2.s
new file mode 100644
index 00000000000..94cec19df49
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2.s
@@ -0,0 +1,138 @@
+/* BFMAX. */
+bfmax {z0.h - z1.h}, {z0.h - z1.h}, z0.h
+bfmax {z30.h - z31.h}, {z30.h - z31.h}, z0.h
+bfmax {z0.h - z1.h}, {z0.h - z1.h}, z15.h
+bfmax {z14.h - z15.h}, {z14.h - z15.h}, z1.h
+bfmax {z6.h - z7.h}, {z6.h - z7.h}, z3.h
+bfmax {z2.h - z3.h}, {z2.h - z3.h}, z7.h
+
+bfmax {z0.h - z3.h}, {z0.h - z3.h}, z0.h
+bfmax {z28.h - z31.h}, {z28.h - z31.h}, z0.h
+bfmax {z0.h - z3.h}, {z0.h - z3.h}, z15.h
+bfmax {z12.h - z15.h}, {z12.h - z15.h}, z1.h
+bfmax {z4.h - z7.h}, {z4.h - z7.h}, z3.h
+bfmax {z4.h - z7.h}, {z4.h - z7.h}, z7.h
+
+/* BFMAX (multiple vectors). */
+bfmax {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfmax {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h}
+bfmax {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h}
+bfmax {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h}
+bfmax {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h}
+bfmax {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h}
+
+bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfmax {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h}
+bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h}
+bfmax {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h}
+bfmax {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h}
+bfmax {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h}
+
+/* BFMAXNM. */
+bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, z0.h
+bfmaxnm {z30.h - z31.h}, {z30.h - z31.h}, z0.h
+bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, z15.h
+bfmaxnm {z14.h - z15.h}, {z14.h - z15.h}, z1.h
+bfmaxnm {z6.h - z7.h}, {z6.h - z7.h}, z3.h
+bfmaxnm {z2.h - z3.h}, {z2.h - z3.h}, z7.h
+
+bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h
+bfmaxnm {z28.h - z31.h}, {z28.h - z31.h}, z0.h
+bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z15.h
+bfmaxnm {z12.h - z15.h}, {z12.h - z15.h}, z1.h
+bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, z3.h
+bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, z7.h
+
+/* BFMAXNM (multiple vectors). */
+bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfmaxnm {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h}
+bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h}
+bfmaxnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h}
+bfmaxnm {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h}
+bfmaxnm {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h}
+
+bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfmaxnm {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h}
+bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h}
+bfmaxnm {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h}
+bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h}
+bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h}
+
+/* BFMIN. */
+bfmin {z0.h - z1.h}, {z0.h - z1.h}, z0.h
+bfmin {z30.h - z31.h}, {z30.h - z31.h}, z0.h
+bfmin {z0.h - z1.h}, {z0.h - z1.h}, z15.h
+bfmin {z14.h - z15.h}, {z14.h - z15.h}, z1.h
+bfmin {z6.h - z7.h}, {z6.h - z7.h}, z3.h
+bfmin {z2.h - z3.h}, {z2.h - z3.h}, z7.h
+
+bfmin {z0.h - z3.h}, {z0.h - z3.h}, z0.h
+bfmin {z28.h - z31.h}, {z28.h - z31.h}, z0.h
+bfmin {z0.h - z3.h}, {z0.h - z3.h}, z15.h
+bfmin {z12.h - z15.h}, {z12.h - z15.h}, z1.h
+bfmin {z4.h - z7.h}, {z4.h - z7.h}, z3.h
+bfmin {z4.h - z7.h}, {z4.h - z7.h}, z7.h
+
+/* BFMIN (multiple vectors). */
+bfmin {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfmin {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h}
+bfmin {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h}
+bfmin {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h}
+bfmin {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h}
+bfmin {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h}
+
+bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfmin {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h}
+bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h}
+bfmin {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h}
+bfmin {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h}
+bfmin {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h}
+
+/* BFMINNM. */
+bfminnm {z0.h - z1.h}, {z0.h - z1.h}, z0.h
+bfminnm {z30.h - z31.h}, {z30.h - z31.h}, z0.h
+bfminnm {z0.h - z1.h}, {z0.h - z1.h}, z15.h
+bfminnm {z14.h - z15.h}, {z14.h - z15.h}, z1.h
+bfminnm {z6.h - z7.h}, {z6.h - z7.h}, z3.h
+bfminnm {z2.h - z3.h}, {z2.h - z3.h}, z7.h
+
+bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h
+bfminnm {z28.h - z31.h}, {z28.h - z31.h}, z0.h
+bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z15.h
+bfminnm {z12.h - z15.h}, {z12.h - z15.h}, z1.h
+bfminnm {z4.h - z7.h}, {z4.h - z7.h}, z3.h
+bfminnm {z4.h - z7.h}, {z4.h - z7.h}, z7.h
+
+/* BFMINNM (multiple vectors). */
+bfminnm {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h}
+bfminnm {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h}
+bfminnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h}
+bfminnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h}
+bfminnm {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h}
+bfminnm {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h}
+
+bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h}
+bfminnm {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h}
+bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h}
+bfminnm {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h}
+bfminnm {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h}
+bfminnm {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h}
+
+/* BFCLAMP. */
+bfclamp {z0.h - z1.h}, z0.h, z0.h
+bfclamp {z30.h - z31.h}, z0.h, z0.h
+bfclamp {z0.h - z1.h}, z31.h, z0.h
+bfclamp {z0.h - z1.h}, z0.h, z31.h
+bfclamp {z14.h - z15.h}, z1.h, z15.h
+bfclamp {z6.h - z7.h}, z3.h, z7.h
+bfclamp {z2.h - z3.h}, z7.h, z3.h
+bfclamp {z20.h - z21.h}, z15.h, z1.h
+
+bfclamp {z0.h - z3.h}, z0.h, z0.h
+bfclamp {z28.h - z31.h}, z0.h, z0.h
+bfclamp {z0.h - z3.h}, z31.h, z0.h
+bfclamp {z0.h - z3.h}, z0.h, z31.h
+bfclamp {z12.h - z15.h}, z1.h, z15.h
+bfclamp {z8.h - z11.h}, z3.h, z7.h
+bfclamp {z4.h - z7.h}, z7.h, z3.h
+bfclamp {z20.h - z23.h}, z15.h, z1.h
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
index 52c7e4a64b5..83f00f55bd0 100644
--- a/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
@@ -183,8 +183,8 @@
.*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d'
.*: Info: did you mean this\?
.*: Info: bfclamp z31.h, z31.h, z31.h
-.*: Error: expected an SVE vector register at operand 1 -- `bfclamp { ?z0.h ?},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfclamp { ?z0.h-z0.h ?},z0.h'
+.*: Error: expected a list of 2 or 4 registers at operand 1 -- `bfclamp { ?z0.h ?},z0.h,z0.h'
+.*: Error: invalid range in vector register list at operand 1 -- `bfclamp { ?z0.h-z0.h ?},z0.h'
.*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h'
.*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]'
.*: Info: did you mean this\?
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 31703ce286a..f9cf325d013 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3312;
+ return 3330;
}
else
{
@@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3314;
+ return 3332;
}
}
else
@@ -235,7 +235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3313;
+ return 3331;
}
else
{
@@ -243,7 +243,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3315;
+ return 3333;
}
}
}
@@ -253,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x0011xxxxxx1xxxxxxxxx
movaz. */
- return 3316;
+ return 3334;
}
}
}
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3444;
+ return 3462;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3445;
+ return 3463;
}
else
{
@@ -318,7 +318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x10xxxxxxxxxxxxxx
luti4. */
- return 3309;
+ return 3327;
}
}
else
@@ -327,7 +327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xx1xxxxxxxxxxxxxx
luti4. */
- return 3308;
+ return 3326;
}
}
}
@@ -369,7 +369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x011xxxxx001xxxxxxxxx
movaz. */
- return 3302;
+ return 3320;
}
else
{
@@ -377,7 +377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x011xxxxx001xxxxxxxxx
movaz. */
- return 3304;
+ return 3322;
}
}
else
@@ -388,7 +388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x011xxxxx001xxxxxxxxx
movaz. */
- return 3303;
+ return 3321;
}
else
{
@@ -396,7 +396,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x011xxxxx001xxxxxxxxx
movaz. */
- return 3305;
+ return 3323;
}
}
}
@@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011000xxx00xxxxxxxxxx
zero. */
- return 3317;
+ return 3335;
}
else
{
@@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011100xxx00xxxxxxxxxx
zero. */
- return 3318;
+ return 3336;
}
}
else
@@ -439,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011010xxx00xxxxxxxxxx
zero. */
- return 3320;
+ return 3338;
}
else
{
@@ -447,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011110xxx00xxxxxxxxxx
zero. */
- return 3323;
+ return 3341;
}
}
}
@@ -461,7 +461,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011001xxx00xxxxxxxxxx
zero. */
- return 3319;
+ return 3337;
}
else
{
@@ -469,7 +469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011101xxx00xxxxxxxxxx
zero. */
- return 3322;
+ return 3340;
}
}
else
@@ -480,7 +480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011011xxx00xxxxxxxxxx
zero. */
- return 3321;
+ return 3339;
}
else
{
@@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011111xxx00xxxxxxxxxx
zero. */
- return 3324;
+ return 3342;
}
}
}
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3446;
+ return 3464;
}
}
else
@@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx0xx00xxxxxxxxxx
luti2. */
- return 3307;
+ return 3325;
}
else
{
@@ -571,7 +571,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx1xx00xxxxxxxxxx
luti2. */
- return 3306;
+ return 3324;
}
}
}
@@ -602,7 +602,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx101xxxxxxxxx
movaz. */
- return 3310;
+ return 3328;
}
}
}
@@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000xx11xxxxx011xxxxxxxxx
movaz. */
- return 3298;
+ return 3316;
}
else
{
@@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100xx11xxxxx011xxxxxxxxx
movaz. */
- return 3300;
+ return 3318;
}
}
else
@@ -658,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010xx11xxxxx011xxxxxxxxx
movaz. */
- return 3299;
+ return 3317;
}
else
{
@@ -666,7 +666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110xx11xxxxx011xxxxxxxxx
movaz. */
- return 3301;
+ return 3319;
}
}
}
@@ -698,7 +698,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx111xxxxxxxxx
movaz. */
- return 3311;
+ return 3329;
}
}
}
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3512;
+ return 3530;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3511;
+ return 3529;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3505;
+ return 3523;
}
}
}
@@ -1754,7 +1754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx00xxxx
fmla. */
- return 3327;
+ return 3345;
}
else
{
@@ -1764,7 +1764,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx000xxxx
fmla. */
- return 3328;
+ return 3346;
}
else
{
@@ -1772,7 +1772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx100xxxx
fdot. */
- return 3490;
+ return 3508;
}
}
}
@@ -1883,7 +1883,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx01xxxx
fmls. */
- return 3333;
+ return 3351;
}
else
{
@@ -1891,7 +1891,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxxx01xxxx
fmls. */
- return 3334;
+ return 3352;
}
}
}
@@ -2135,7 +2135,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3325;
+ return 3343;
}
}
else
@@ -2179,7 +2179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3504;
+ return 3522;
}
}
}
@@ -2284,7 +2284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3497;
+ return 3515;
}
}
}
@@ -2330,7 +2330,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx11xxx
fmops. */
- return 3326;
+ return 3344;
}
}
else
@@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3496;
+ return 3514;
}
}
}
@@ -2510,7 +2510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3503;
+ return 3521;
}
else
{
@@ -2878,7 +2878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3483;
+ return 3501;
}
else
{
@@ -2947,7 +2947,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3484;
+ return 3502;
}
else
{
@@ -3026,7 +3026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3495;
+ return 3513;
}
else
{
@@ -3081,7 +3081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3514;
+ return 3532;
}
else
{
@@ -3099,7 +3099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3489;
+ return 3507;
}
}
}
@@ -3173,7 +3173,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3513;
+ return 3531;
}
}
}
@@ -3253,7 +3253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3515;
+ return 3533;
}
else
{
@@ -3430,7 +3430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3509;
+ return 3527;
}
else
{
@@ -3438,7 +3438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3510;
+ return 3528;
}
}
}
@@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3507;
+ return 3525;
}
else
{
@@ -3501,7 +3501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3508;
+ return 3526;
}
}
}
@@ -3555,7 +3555,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3493;
+ return 3511;
}
else
{
@@ -3563,7 +3563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3494;
+ return 3512;
}
}
}
@@ -3625,7 +3625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3501;
+ return 3519;
}
else
{
@@ -3633,7 +3633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3502;
+ return 3520;
}
}
}
@@ -3688,7 +3688,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3499;
+ return 3517;
}
else
{
@@ -3696,7 +3696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3500;
+ return 3518;
}
}
}
@@ -3765,7 +3765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3506;
+ return 3524;
}
}
else
@@ -3848,7 +3848,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3498;
+ return 3516;
}
}
else
@@ -3861,7 +3861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx111xxxxx00xxx
fmla. */
- return 3329;
+ return 3347;
}
else
{
@@ -3881,7 +3881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x00xx111xxxxx00xxx
fadd. */
- return 3447;
+ return 3465;
}
}
else
@@ -3900,7 +3900,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x10xx111xxxxx00xxx
fadd. */
- return 3448;
+ return 3466;
}
}
}
@@ -3911,7 +3911,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx111xxxxx00xxx
fmla. */
- return 3330;
+ return 3348;
}
}
}
@@ -4036,7 +4036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3487;
+ return 3505;
}
else
{
@@ -4044,7 +4044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3488;
+ return 3506;
}
}
}
@@ -4337,7 +4337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx100xxxxx01xxx
fdot. */
- return 3491;
+ return 3509;
}
else
{
@@ -4345,7 +4345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx100xxxxx01xxx
fdot. */
- return 3492;
+ return 3510;
}
}
else
@@ -4356,7 +4356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxxx01xxx
fmla. */
- return 3331;
+ return 3349;
}
else
{
@@ -4364,7 +4364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxxx01xxx
fmla. */
- return 3332;
+ return 3350;
}
}
}
@@ -4628,7 +4628,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx111xxxxx01xxx
fmls. */
- return 3335;
+ return 3353;
}
else
{
@@ -4648,7 +4648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x00xx111xxxxx01xxx
fsub. */
- return 3449;
+ return 3467;
}
}
else
@@ -4667,7 +4667,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x10xx111xxxxx01xxx
fsub. */
- return 3450;
+ return 3468;
}
}
}
@@ -4678,7 +4678,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx111xxxxx01xxx
fmls. */
- return 3336;
+ return 3354;
}
}
}
@@ -4741,7 +4741,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx100xxxxx11xxx
fdot. */
- return 3485;
+ return 3503;
}
else
{
@@ -4749,7 +4749,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx100xxxxx11xxx
fdot. */
- return 3486;
+ return 3504;
}
}
else
@@ -4760,7 +4760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxxx11xxx
fmls. */
- return 3337;
+ return 3355;
}
else
{
@@ -4768,7 +4768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxxx11xxx
fmls. */
- return 3338;
+ return 3356;
}
}
}
@@ -5304,7 +5304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3421;
+ return 3439;
}
}
else
@@ -5430,7 +5430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101x0000111000xxxxxxxxx0
fcvt. */
- return 3339;
+ return 3357;
}
else
{
@@ -5438,7 +5438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101x0000111000xxxxxxxxx1
fcvtl. */
- return 3340;
+ return 3358;
}
}
}
@@ -5496,7 +5496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3418;
+ return 3436;
}
else
{
@@ -5504,7 +5504,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3413;
+ return 3431;
}
}
else
@@ -5513,7 +5513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3419;
+ return 3437;
}
}
else
@@ -5542,7 +5542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3420;
+ return 3438;
}
}
}
@@ -5625,7 +5625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3414;
+ return 3432;
}
else
{
@@ -5633,7 +5633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3415;
+ return 3433;
}
}
else
@@ -5644,7 +5644,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3409;
+ return 3427;
}
else
{
@@ -5652,7 +5652,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3410;
+ return 3428;
}
}
}
@@ -5687,7 +5687,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3416;
+ return 3434;
}
[...]
[diff truncated at 100000 bytes]
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