[binutils-gdb] aarch64: rcpc3: New RCPC3_ADDR operand types
Victor Do Nascimento
victorldn@sourceware.org
Mon Jan 15 13:16:32 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=51bb8593e6f533970385ca64f40a5bbfc82285da
commit 51bb8593e6f533970385ca64f40a5bbfc82285da
Author: Victor Do Nascimento <victor.donascimento@arm.com>
Date: Fri Jan 5 17:26:09 2024 +0000
aarch64: rcpc3: New RCPC3_ADDR operand types
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Diff:
---
gas/config/tc-aarch64.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++
include/opcode/aarch64.h | 5 ++++
opcodes/aarch64-opc.c | 5 ++++
opcodes/aarch64-tbl.h | 16 +++++++++++-
4 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6b296837b68..0c6de289408 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7269,7 +7269,52 @@ parse_operands (char *str, const aarch64_opcode *opcode)
inst.reloc.pc_rel = 1;
}
break;
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.writeback)
+ {
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+ }
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ {
+ char *start = str;
+ /* First use the normal address-parsing routines, to get
+ the usual syntax errors. */
+ po_misc_or_fail (parse_address (&str, info));
+ if ((operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
+ && info->addr.writeback && info->addr.preind)
+ || (operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
+ && info->addr.writeback && info->addr.postind))
+ {
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+ }
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ /* Then retry, matching the specific syntax of these addresses. */
+ str = start;
+ po_char_or_fail ('[');
+ po_reg_or_fail (REG_TYPE_R64_SP);
+ po_char_or_fail (']');
+ break;
+ }
case AARCH64_OPND_ADDR_SIMPLE:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
@@ -7390,6 +7435,26 @@ parse_operands (char *str, const aarch64_opcode *opcode)
/* skip_p */ 0);
break;
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (inst.reloc.type != BFD_RELOC_UNUSED)
+ {
+ set_syntax_error (_("relocation not allowed"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+
case AARCH64_OPND_ADDR_UIMM12:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 85e28d9d287..44d6aafd4b3 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -799,6 +799,11 @@ enum aarch64_opnd
AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */
AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */
AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */
+ AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* [<Xn|SP>]{, #<imm>}. */
+ AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */
+ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
+ AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */
+ AARCH64_OPND_RCPC3_ADDR_OFFSET
};
/* Qualifier constrains an operand. It either specifies a variant of an
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 9a72d30268f..06d74870cba 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4588,7 +4588,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_ADDR_SIMM10:
case AARCH64_OPND_ADDR_SIMM11:
case AARCH64_OPND_ADDR_SIMM13:
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
case AARCH64_OPND_ADDR_OFFSET:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
case AARCH64_OPND_SME_ADDR_RI_U4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 149265a6397..1092d63ebc5 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -7025,4 +7025,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a list of 3 SVE vector registers") \
X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4", \
4 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \
- "a list of 4 SVE vector registers")
+ "a list of 4 SVE vector registers") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \
+ "an address with post-incrementing by ammount of loaded bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD_opc2), \
+ "an address with pre-incrementing with write-back by ammount of stored bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_POSTIND", 0, F(), \
+ "an address with post-incrementing by ammount of loaded bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_PREIND_WB", 0, F(), \
+ "an address with pre-incrementing with write-back by ammount of stored bytes") \
+ Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \
+ "an address with an optional 8-bit signed immediate offset")
More information about the Binutils-cvs
mailing list