[binutils-gdb] MIPS/opcodes: Disassemble the RFE instruction

[Maciej W. Rozycki]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b930964c425533f2344c6b26d4af17200bb42928

commit b930964c425533f2344c6b26d4af17200bb42928
Author: Maciej W. Rozycki <macro@orcam.me.uk>
Date:   Sat May 29 03:26:32 2021 +0200

    MIPS/opcodes: Disassemble the RFE instruction
    
    Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
    <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
    and bring the disassembly of the RFE instruction back for the relevant
    ISA levels.
    
    It is because the "rfe" opcode table entry was incorrectly moved behind
    the catch-all generic "c0" entry for CP0 instructions, causing output
    like:
    
      00:   42000010        c0      0x10
    
    to be produced rather than:
    
      00:   42000010        rfe
    
    even for ISA levels that do include the RFE instruction.
    
    Move the "rfe" entry ahead of "c0" then, correcting the problem.  Add a
    suitable test case.
    
            opcodes/
            * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
            of "c0".
    
            gas/
            * testsuite/gas/mips/rfe.d: New test.
            * testsuite/gas/mips/rfe.s: New test source.
            * testsuite/gas/mips/mips.exp: Run the new test.

Diff:
---
 gas/ChangeLog                   | 6 ++++++
 gas/testsuite/gas/mips/mips.exp | 3 +++
 gas/testsuite/gas/mips/rfe.d    | 9 +++++++++
 gas/testsuite/gas/mips/rfe.s    | 8 ++++++++
 opcodes/ChangeLog               | 5 +++++
 opcodes/mips-opc.c              | 5 +++--
 6 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 89a1acd2768..b4b6387d46f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+	* testsuite/gas/mips/rfe.d: New test.
+	* testsuite/gas/mips/rfe.s: New test source.
+	* testsuite/gas/mips/mips.exp: Run the new test.
+
 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 
 	* testsuite/gas/mips/cp1-names-r3900.d: New test.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index aebfe3d05bb..65a74dd9b67 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1338,6 +1338,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "cp0m"		[mips_arch_list_matching mips1 \
 					    !mips2 !micromips]
 
+    run_dump_test_arches "rfe"		[mips_arch_list_matching mips1 \
+					    !mips3 !mips32 !micromips]
+
     run_dump_test "cp1-names-numeric"
     run_dump_test "cp1-names-r3000"
     run_dump_test "cp1-names-r3900"
diff --git a/gas/testsuite/gas/mips/rfe.d b/gas/testsuite/gas/mips/rfe.d
new file mode 100644
index 00000000000..c086e9db702
--- /dev/null
+++ b/gas/testsuite/gas/mips/rfe.d
@@ -0,0 +1,9 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000010 	rfe
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/rfe.s b/gas/testsuite/gas/mips/rfe.s
new file mode 100644
index 00000000000..9094a571b93
--- /dev/null
+++ b/gas/testsuite/gas/mips/rfe.s
@@ -0,0 +1,8 @@
+	.text
+	.set	noreorder
+foo:
+	rfe
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 795391d61b5..2e93d56aa0c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+	* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
+	of "c0".
+
 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 
 	* mips-dis.c (mips_cp1_names_mips): New variable.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 812fcc6da87..210d0149920 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -3399,6 +3399,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ginvi",		"s",		0x7c00003d, 0xfc1fffff, RD_1,			0,		0,		GINV,	0 },
 {"ginvt",		"s,+\\",	0x7c0000bd, 0xfc1ffcff, RD_1,			0,		0,		GINV,	0 },
 
+/* RFE conflicts with the new Virt spec instruction tlbgp. */
+{"rfe",			"",		0x42000010, 0xffffffff,	0,			0,		I1|T3,		0,	0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
@@ -3411,8 +3414,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cop1",		"C",		0,    (int) M_COP1,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	0 },
 {"cop2",		"C",		0,    (int) M_COP2,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
 {"cop3",		"C",		0,    (int) M_COP3,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-/* RFE conflicts with the new Virt spec instruction tlbgp. */
-{"rfe",			"",		0x42000010, 0xffffffff,	0,			0,		I1|T3,		0,	0 },
 };
 
 #define MIPS_NUM_OPCODES \