[binutils-gdb] MIPS/opcodes: Properly handle ISA exclusion

[Maciej W. Rozycki]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=21629cf8bc2b16d3c75dff0c3f1222b714bf90c2

commit 21629cf8bc2b16d3c75dff0c3f1222b714bf90c2
Author: Maciej W. Rozycki <macro@orcam.me.uk>
Date:   Sat May 29 03:26:32 2021 +0200

    MIPS/opcodes: Properly handle ISA exclusion
    
    Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
    handle the exclusion for any ISA levels properly in `opcode_is_member'.
    Flatten the structure of the `if' statements there.  No functional
    change for the existing opcode tables.
    
            include/
            * opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
            exclusion.
            (opcode_is_member): Handle ISA level exclusion.

Diff:
---
 include/ChangeLog     |  6 ++++++
 include/opcode/mips.h | 37 ++++++++++++++++++-------------------
 2 files changed, 24 insertions(+), 19 deletions(-)

diff --git a/include/ChangeLog b/include/ChangeLog
index b51782f5093..d1a0485fb12 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+	* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
+	exclusion.
+	(opcode_is_member): Handle ISA level exclusion.
+
 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 
 	* opcode/mips.h (isa_is_member): New inline function, factored
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index aa6e9d7cee9..9add3c9d5bf 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1459,13 +1459,6 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_INTERAPTIV_MR2:
       return (mask & INSN_INTERAPTIV_MR2) != 0;
 
-    case CPU_MIPS32R6:
-      return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
-
-    case CPU_MIPS64R6:
-      return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
-	     || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
-
     default:
       return false;
     }
@@ -1500,20 +1493,26 @@ isa_is_member (int isa, unsigned int mask)
 static inline bool
 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 {
-  if (!cpu_is_member (cpu, insn->exclusions))
-    {
-      /* Test for ISA level compatibility.  */
-      if (isa_is_member (isa, insn->membership))
-	return true;
+  /* Test for ISA level exclusion.  */
+  if (isa_is_member (isa, insn->exclusions))
+    return false;
 
-      /* Test for ASE compatibility.  */
-      if ((ase & insn->ase) != 0)
-	return true;
+  /* Test for processor-specific exclusion.  */
+  if (cpu_is_member (cpu, insn->exclusions))
+    return false;
+
+  /* Test for ISA level compatibility.  */
+  if (isa_is_member (isa, insn->membership))
+    return true;
+
+  /* Test for ASE compatibility.  */
+  if ((ase & insn->ase) != 0)
+    return true;
+
+  /* Test for processor-specific extensions.  */
+  if (cpu_is_member (cpu, insn->membership))
+    return true;
 
-      /* Test for processor-specific extensions.  */
-      if (cpu_is_member (cpu, insn->membership))
-	return true;
-    }
   return false;
 }