[binutils-gdb] [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
Sudakshina Das
sudi@sourceware.org
Mon Nov 12 13:31:00 GMT 2018
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=fb3265b371a141c4ffc97dcf8cc66e090c516dc8
commit fb3265b371a141c4ffc97dcf8cc66e090c516dc8
Author: Sudakshina Das <sudi.das@arm.com>
Date: Mon Nov 12 13:09:55 2018 +0000
[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Diff:
---
gas/ChangeLog | 12 +
gas/config/tc-aarch64.c | 6 +
gas/testsuite/gas/aarch64/armv8_5-a-memtag.d | 58 +
gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | 34 +
gas/testsuite/gas/aarch64/illegal-memtag.l | 13 +
gas/testsuite/gas/aarch64/illegal-memtag.s | 17 +
include/ChangeLog | 6 +
include/opcode/aarch64.h | 8 +
opcodes/ChangeLog | 15 +
opcodes/aarch64-asm-2.c | 774 +++----
opcodes/aarch64-asm.c | 3 +-
opcodes/aarch64-dis-2.c | 2960 +++++++++++++-------------
opcodes/aarch64-dis.c | 3 +-
opcodes/aarch64-opc-2.c | 76 +-
opcodes/aarch64-opc.c | 35 +
opcodes/aarch64-tbl.h | 27 +
16 files changed, 2198 insertions(+), 1849 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 784a638..57a3c38 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,17 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
+ * config/tc-aarch64.c (parse_operands): Add switch case for
+ AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
+ (fix_insn): Likewise.
+ (warn_unpredictable_ldst): Exempt STGP.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
+ stzg, stz2g and stgp.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
subps and cmpp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5f79e92..a5eee96 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6214,6 +6214,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_ADDR_SIMM9:
case AARCH64_OPND_ADDR_SIMM9_2:
+ case AARCH64_OPND_ADDR_SIMM11:
+ case AARCH64_OPND_ADDR_SIMM13:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
|| (!info->addr.preind && !info->addr.postind)
@@ -6773,6 +6775,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
&& (opnds[0].reg.regno == opnds[2].addr.base_regno
|| opnds[1].reg.regno == opnds[2].addr.base_regno)
&& opnds[2].addr.base_regno != REG_SP
+ /* Exempt STGP. */
+ && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)
&& opnds[2].addr.writeback)
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
/* Load operations must load different registers. */
@@ -7674,6 +7678,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
case AARCH64_OPND_ADDR_SIMM9_2:
case AARCH64_OPND_ADDR_SIMM10:
case AARCH64_OPND_ADDR_UIMM12:
+ case AARCH64_OPND_ADDR_SIMM11:
+ case AARCH64_OPND_ADDR_SIMM13:
/* Immediate offset in an address. */
insn = get_aarch64_insn (buf);
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index a7cb6c4..4140646 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -55,3 +55,61 @@ Disassembly of section \.text:
.*: badb037f cmpp x27, x27
.*: bac003ff cmpp sp, x0
.*: badf001f cmpp x0, sp
+.*: d920081f stg \[x0\]
+.*: d9200b7f stg \[x27\]
+.*: d93fb81f stg \[x0, #-80\]
+.*: d9200c1f stg \[x0, #0\]!
+.*: d920ac1f stg \[x0, #160\]!
+.*: d920041f stg \[x0\], #0
+.*: d93a641f stg \[x0\], #-1440
+.*: d92ffbff stg \[sp, #4080\]
+.*: d9300bff stg \[sp, #-4096\]
+.*: d92fffff stg \[sp, #4080\]!
+.*: d93007ff stg \[sp\], #-4096
+.*: d960081f stzg \[x0\]
+.*: d9600b7f stzg \[x27\]
+.*: d97fb81f stzg \[x0, #-80\]
+.*: d9600c1f stzg \[x0, #0\]!
+.*: d960ac1f stzg \[x0, #160\]!
+.*: d960041f stzg \[x0\], #0
+.*: d97a641f stzg \[x0\], #-1440
+.*: d96ffbff stzg \[sp, #4080\]
+.*: d9700bff stzg \[sp, #-4096\]
+.*: d96fffff stzg \[sp, #4080\]!
+.*: d97007ff stzg \[sp\], #-4096
+.*: d9a0081f st2g \[x0\]
+.*: d9a00b7f st2g \[x27\]
+.*: d9bfb81f st2g \[x0, #-80\]
+.*: d9a00c1f st2g \[x0, #0\]!
+.*: d9a0ac1f st2g \[x0, #160\]!
+.*: d9a0041f st2g \[x0\], #0
+.*: d9ba641f st2g \[x0\], #-1440
+.*: d9affbff st2g \[sp, #4080\]
+.*: d9b00bff st2g \[sp, #-4096\]
+.*: d9afffff st2g \[sp, #4080\]!
+.*: d9b007ff st2g \[sp\], #-4096
+.*: d9e0081f stz2g \[x0\]
+.*: d9e00b7f stz2g \[x27\]
+.*: d9ffb81f stz2g \[x0, #-80\]
+.*: d9e00c1f stz2g \[x0, #0\]!
+.*: d9e0ac1f stz2g \[x0, #160\]!
+.*: d9e0041f stz2g \[x0\], #0
+.*: d9fa641f stz2g \[x0\], #-1440
+.*: d9effbff stz2g \[sp, #4080\]
+.*: d9f00bff stz2g \[sp, #-4096\]
+.*: d9efffff stz2g \[sp, #4080\]!
+.*: d9f007ff stz2g \[sp\], #-4096
+.*: 69000000 stgp x0, x0, \[x0\]
+.*: 69006c00 stgp x0, x27, \[x0\]
+.*: 6900001b stgp x27, x0, \[x0\]
+.*: 69006c1b stgp x27, x27, \[x0\]
+.*: 69000360 stgp x0, x0, \[x27\]
+.*: 693d8000 stgp x0, x0, \[x0, #-80\]
+.*: 69800000 stgp x0, x0, \[x0, #0\]!
+.*: 69850000 stgp x0, x0, \[x0, #160\]!
+.*: 68800000 stgp x0, x0, \[x0\], #0
+.*: 68bb8000 stgp x0, x0, \[x0\], #-144
+.*: 691f801f stgp xzr, x0, \[x0, #1008\]
+.*: 69207c00 stgp x0, xzr, \[x0, #-1024\]
+.*: 699f83e0 stgp x0, x0, \[sp, #1008\]!
+.*: 68a003e0 stgp x0, x0, \[sp\], #-1024
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index f17f87e..729dae6 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -16,6 +16,20 @@ func:
\op x27, x27, #0, #0
.endm
+ .macro expand_stg op
+ \op [x0, #0]
+ \op [x27, #0]
+ \op [x0, #-80]
+ \op [x0, #0]!
+ \op [x0, #160]!
+ \op [x0], #0
+ \op [x0], #-1440
+ \op [sp, #4080]
+ \op [sp, #-4096]
+ \op [sp, #4080]!
+ \op [sp], #-4096
+ .endm
+
# IRG
expand_3_reg irg
irg sp, x0
@@ -55,3 +69,23 @@ func:
cmpp x27, x27
cmpp sp, x0
cmpp x0, sp
+
+ expand_stg stg
+ expand_stg stzg
+ expand_stg st2g
+ expand_stg stz2g
+
+ stgp x0, x0, [x0, #0]
+ stgp x0, x27, [x0, #0]
+ stgp x27, x0, [x0, #0]
+ stgp x27, x27, [x0, #0]
+ stgp x0, x0, [x27, #0]
+ stgp x0, x0, [x0, #-80]
+ stgp x0, x0, [x0, #0]!
+ stgp x0, x0, [x0, #160]!
+ stgp x0, x0, [x0], #0
+ stgp x0, x0, [x0], #-144
+ stgp xzr, x0, [x0, #1008]
+ stgp x0, xzr, [x0, #-1024]
+ stgp x0, x0, [sp, #1008]!
+ stgp x0, x0, [sp], #-1024
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 4da0c35..dd568cc 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -4,6 +4,12 @@
[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
+[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]'
+[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!'
+[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096'
+[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
+[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
+[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -20,3 +26,10 @@
[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stg \[xzr,#0\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `st2g \[xzr,#0]!'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stzg \[xzr],#0'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stz2g \[xzr,#0\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
+[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 7eab07f..2a66366 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -8,6 +8,16 @@ func:
addg x1, x2, #0x3f0, #0x10
subg x1, x2, #0x3f0, -4
+ # STG/STZG/ST2G : Fail imm
+ stg [x1, #15]
+ stzg [x1, #-4097]!
+ st2g [x1], #4096
+
+ # STGP : Fail imm
+ stgp x1, x2, [x3, #1009]
+ stgp x1, x2, [x3, #33]
+ stgp x1, x2, [x3, #-1025]
+
# Illegal SP/XZR registers
irg xzr, x2, x3
irg x1, xzr, x3
@@ -25,3 +35,10 @@ func:
subps x1, x2, xzr
cmpp xzr, x2
cmpp x2, xzr
+ stg [xzr, #0]
+ st2g [xzr, #0]!
+ stzg [xzr], #0
+ stz2g [xzr, #0]
+ stgp sp, x2, [x3]
+ stgp x1, sp, [x3]
+ stgp x0, x0, [xzr]
diff --git a/include/ChangeLog b/include/ChangeLog
index 2bdee25..491bbd4 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,11 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
+ * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
+ and AARCH64_OPND_ADDR_SIMM13.
+ (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d6e639d..c4c573a 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -286,7 +286,11 @@ enum aarch64_opnd
the mnemonic name for LDUR/STUR instructions
wherever there is no ambiguity. */
AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
+ AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
+ 16) immediate. */
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
+ AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
+ 16) immediate. */
AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
@@ -467,6 +471,10 @@ enum aarch64_opnd_qualifier
AARCH64_OPND_QLF_P_Z,
AARCH64_OPND_QLF_P_M,
+ /* Used in scaled signed immediate that are scaled by a Tag granule
+ like in stg, st2g, etc. */
+ AARCH64_OPND_QLF_imm_tag,
+
/* Constraint on value. */
AARCH64_OPND_QLF_CR, /* CRn, CRm. */
AARCH64_OPND_QLF_imm_0_7,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 424368c..df21eeb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,20 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
+ * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
+ for AARCH64_OPND_QLF_imm_tag.
+ (operand_general_constraint_met_p): Add case for
+ AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
+ (aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
+ (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
+ for both offset and pre/post indexed versions.
+ (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 1310260..67d480a 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -201,390 +201,390 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 757: /* extr */
value = 757; /* --> extr. */
break;
- case 977: /* bic */
- case 976: /* and */
- value = 976; /* --> and. */
- break;
- case 979: /* mov */
- case 978: /* orr */
- value = 978; /* --> orr. */
- break;
- case 982: /* tst */
- case 981: /* ands */
- value = 981; /* --> ands. */
- break;
- case 987: /* uxtw */
- case 986: /* mov */
- case 985: /* orr */
- value = 985; /* --> orr. */
+ case 987: /* bic */
+ case 986: /* and */
+ value = 986; /* --> and. */
+ break;
+ case 989: /* mov */
+ case 988: /* orr */
+ value = 988; /* --> orr. */
+ break;
+ case 992: /* tst */
+ case 991: /* ands */
+ value = 991; /* --> ands. */
+ break;
+ case 997: /* uxtw */
+ case 996: /* mov */
+ case 995: /* orr */
+ value = 995; /* --> orr. */
break;
- case 989: /* mvn */
- case 988: /* orn */
- value = 988; /* --> orn. */
+ case 999: /* mvn */
+ case 998: /* orn */
+ value = 998; /* --> orn. */
break;
- case 993: /* tst */
- case 992: /* ands */
- value = 992; /* --> ands. */
+ case 1003: /* tst */
+ case 1002: /* ands */
+ value = 1002; /* --> ands. */
break;
- case 1119: /* staddb */
- case 1023: /* ldaddb */
- value = 1023; /* --> ldaddb. */
+ case 1129: /* staddb */
+ case 1033: /* ldaddb */
+ value = 1033; /* --> ldaddb. */
break;
- case 1120: /* staddh */
- case 1024: /* ldaddh */
- value = 1024; /* --> ldaddh. */
+ case 1130: /* staddh */
+ case 1034: /* ldaddh */
+ value = 1034; /* --> ldaddh. */
break;
- case 1121: /* stadd */
- case 1025: /* ldadd */
- value = 1025; /* --> ldadd. */
+ case 1131: /* stadd */
+ case 1035: /* ldadd */
+ value = 1035; /* --> ldadd. */
break;
- case 1122: /* staddlb */
- case 1027: /* ldaddlb */
- value = 1027; /* --> ldaddlb. */
+ case 1132: /* staddlb */
+ case 1037: /* ldaddlb */
+ value = 1037; /* --> ldaddlb. */
break;
- case 1123: /* staddlh */
- case 1030: /* ldaddlh */
- value = 1030; /* --> ldaddlh. */
+ case 1133: /* staddlh */
+ case 1040: /* ldaddlh */
+ value = 1040; /* --> ldaddlh. */
break;
- case 1124: /* staddl */
- case 1033: /* ldaddl */
- value = 1033; /* --> ldaddl. */
+ case 1134: /* staddl */
+ case 1043: /* ldaddl */
+ value = 1043; /* --> ldaddl. */
break;
- case 1125: /* stclrb */
- case 1035: /* ldclrb */
- value = 1035; /* --> ldclrb. */
+ case 1135: /* stclrb */
+ case 1045: /* ldclrb */
+ value = 1045; /* --> ldclrb. */
break;
- case 1126: /* stclrh */
- case 1036: /* ldclrh */
- value = 1036; /* --> ldclrh. */
+ case 1136: /* stclrh */
+ case 1046: /* ldclrh */
+ value = 1046; /* --> ldclrh. */
break;
- case 1127: /* stclr */
- case 1037: /* ldclr */
- value = 1037; /* --> ldclr. */
+ case 1137: /* stclr */
+ case 1047: /* ldclr */
+ value = 1047; /* --> ldclr. */
break;
- case 1128: /* stclrlb */
- case 1039: /* ldclrlb */
- value = 1039; /* --> ldclrlb. */
+ case 1138: /* stclrlb */
+ case 1049: /* ldclrlb */
+ value = 1049; /* --> ldclrlb. */
break;
- case 1129: /* stclrlh */
- case 1042: /* ldclrlh */
- value = 1042; /* --> ldclrlh. */
+ case 1139: /* stclrlh */
+ case 1052: /* ldclrlh */
+ value = 1052; /* --> ldclrlh. */
break;
- case 1130: /* stclrl */
- case 1045: /* ldclrl */
- value = 1045; /* --> ldclrl. */
+ case 1140: /* stclrl */
+ case 1055: /* ldclrl */
+ value = 1055; /* --> ldclrl. */
break;
- case 1131: /* steorb */
- case 1047: /* ldeorb */
- value = 1047; /* --> ldeorb. */
+ case 1141: /* steorb */
+ case 1057: /* ldeorb */
+ value = 1057; /* --> ldeorb. */
break;
- case 1132: /* steorh */
- case 1048: /* ldeorh */
- value = 1048; /* --> ldeorh. */
+ case 1142: /* steorh */
+ case 1058: /* ldeorh */
+ value = 1058; /* --> ldeorh. */
break;
- case 1133: /* steor */
- case 1049: /* ldeor */
- value = 1049; /* --> ldeor. */
+ case 1143: /* steor */
+ case 1059: /* ldeor */
+ value = 1059; /* --> ldeor. */
break;
- case 1134: /* steorlb */
- case 1051: /* ldeorlb */
- value = 1051; /* --> ldeorlb. */
+ case 1144: /* steorlb */
+ case 1061: /* ldeorlb */
+ value = 1061; /* --> ldeorlb. */
break;
- case 1135: /* steorlh */
- case 1054: /* ldeorlh */
- value = 1054; /* --> ldeorlh. */
+ case 1145: /* steorlh */
+ case 1064: /* ldeorlh */
+ value = 1064; /* --> ldeorlh. */
break;
- case 1136: /* steorl */
- case 1057: /* ldeorl */
- value = 1057; /* --> ldeorl. */
+ case 1146: /* steorl */
+ case 1067: /* ldeorl */
+ value = 1067; /* --> ldeorl. */
break;
- case 1137: /* stsetb */
- case 1059: /* ldsetb */
- value = 1059; /* --> ldsetb. */
+ case 1147: /* stsetb */
+ case 1069: /* ldsetb */
+ value = 1069; /* --> ldsetb. */
break;
- case 1138: /* stseth */
- case 1060: /* ldseth */
- value = 1060; /* --> ldseth. */
+ case 1148: /* stseth */
+ case 1070: /* ldseth */
+ value = 1070; /* --> ldseth. */
break;
- case 1139: /* stset */
- case 1061: /* ldset */
- value = 1061; /* --> ldset. */
+ case 1149: /* stset */
+ case 1071: /* ldset */
+ value = 1071; /* --> ldset. */
break;
- case 1140: /* stsetlb */
- case 1063: /* ldsetlb */
- value = 1063; /* --> ldsetlb. */
+ case 1150: /* stsetlb */
+ case 1073: /* ldsetlb */
+ value = 1073; /* --> ldsetlb. */
break;
- case 1141: /* stsetlh */
- case 1066: /* ldsetlh */
- value = 1066; /* --> ldsetlh. */
+ case 1151: /* stsetlh */
+ case 1076: /* ldsetlh */
+ value = 1076; /* --> ldsetlh. */
break;
- case 1142: /* stsetl */
- case 1069: /* ldsetl */
- value = 1069; /* --> ldsetl. */
+ case 1152: /* stsetl */
+ case 1079: /* ldsetl */
+ value = 1079; /* --> ldsetl. */
break;
- case 1143: /* stsmaxb */
- case 1071: /* ldsmaxb */
- value = 1071; /* --> ldsmaxb. */
+ case 1153: /* stsmaxb */
+ case 1081: /* ldsmaxb */
+ value = 1081; /* --> ldsmaxb. */
break;
- case 1144: /* stsmaxh */
- case 1072: /* ldsmaxh */
- value = 1072; /* --> ldsmaxh. */
+ case 1154: /* stsmaxh */
+ case 1082: /* ldsmaxh */
+ value = 1082; /* --> ldsmaxh. */
break;
- case 1145: /* stsmax */
- case 1073: /* ldsmax */
- value = 1073; /* --> ldsmax. */
- break;
- case 1146: /* stsmaxlb */
- case 1075: /* ldsmaxlb */
- value = 1075; /* --> ldsmaxlb. */
- break;
- case 1147: /* stsmaxlh */
- case 1078: /* ldsmaxlh */
- value = 1078; /* --> ldsmaxlh. */
- break;
- case 1148: /* stsmaxl */
- case 1081: /* ldsmaxl */
- value = 1081; /* --> ldsmaxl. */
- break;
- case 1149: /* stsminb */
- case 1083: /* ldsminb */
- value = 1083; /* --> ldsminb. */
- break;
- case 1150: /* stsminh */
- case 1084: /* ldsminh */
- value = 1084; /* --> ldsminh. */
- break;
- case 1151: /* stsmin */
- case 1085: /* ldsmin */
- value = 1085; /* --> ldsmin. */
- break;
- case 1152: /* stsminlb */
- case 1087: /* ldsminlb */
- value = 1087; /* --> ldsminlb. */
- break;
- case 1153: /* stsminlh */
- case 1090: /* ldsminlh */
- value = 1090; /* --> ldsminlh. */
- break;
- case 1154: /* stsminl */
- case 1093: /* ldsminl */
- value = 1093; /* --> ldsminl. */
- break;
- case 1155: /* stumaxb */
- case 1095: /* ldumaxb */
- value = 1095; /* --> ldumaxb. */
- break;
- case 1156: /* stumaxh */
- case 1096: /* ldumaxh */
- value = 1096; /* --> ldumaxh. */
- break;
- case 1157: /* stumax */
- case 1097: /* ldumax */
- value = 1097; /* --> ldumax. */
- break;
- case 1158: /* stumaxlb */
- case 1099: /* ldumaxlb */
- value = 1099; /* --> ldumaxlb. */
- break;
- case 1159: /* stumaxlh */
- case 1102: /* ldumaxlh */
- value = 1102; /* --> ldumaxlh. */
- break;
- case 1160: /* stumaxl */
- case 1105: /* ldumaxl */
- value = 1105; /* --> ldumaxl. */
- break;
- case 1161: /* stuminb */
- case 1107: /* lduminb */
- value = 1107; /* --> lduminb. */
- break;
- case 1162: /* stuminh */
- case 1108: /* lduminh */
- value = 1108; /* --> lduminh. */
- break;
- case 1163: /* stumin */
- case 1109: /* ldumin */
- value = 1109; /* --> ldumin. */
- break;
- case 1164: /* stuminlb */
- case 1111: /* lduminlb */
- value = 1111; /* --> lduminlb. */
- break;
- case 1165: /* stuminlh */
- case 1114: /* lduminlh */
- value = 1114; /* --> lduminlh. */
- break;
- case 1166: /* stuminl */
- case 1117: /* lduminl */
- value = 1117; /* --> lduminl. */
- break;
- case 1168: /* mov */
- case 1167: /* movn */
- value = 1167; /* --> movn. */
- break;
- case 1170: /* mov */
- case 1169: /* movz */
- value = 1169; /* --> movz. */
- break;
- case 1216: /* autibsp */
- case 1215: /* autibz */
- case 1214: /* autiasp */
- case 1213: /* autiaz */
- case 1212: /* pacibsp */
- case 1211: /* pacibz */
- case 1210: /* paciasp */
- case 1209: /* paciaz */
- case 1190: /* psb */
- case 1189: /* esb */
- case 1188: /* autib1716 */
- case 1187: /* autia1716 */
- case 1186: /* pacib1716 */
- case 1185: /* pacia1716 */
- case 1184: /* xpaclri */
- case 1183: /* sevl */
- case 1182: /* sev */
- case 1181: /* wfi */
- case 1180: /* wfe */
- case 1179: /* yield */
- case 1178: /* bti */
- case 1177: /* csdb */
- case 1176: /* nop */
- case 1175: /* hint */
- value = 1175; /* --> hint. */
- break;
- case 1194: /* pssbb */
- case 1193: /* ssbb */
- case 1192: /* dsb */
- value = 1192; /* --> dsb. */
- break;
- case 1205: /* cpp */
- case 1204: /* dvp */
- case 1203: /* cfp */
- case 1202: /* tlbi */
- case 1201: /* ic */
- case 1200: /* dc */
- case 1199: /* at */
- case 1198: /* sys */
- value = 1198; /* --> sys. */
- break;
- case 2014: /* bic */
- case 1264: /* and */
- value = 1264; /* --> and. */
+ case 1155: /* stsmax */
+ case 1083: /* ldsmax */
+ value = 1083; /* --> ldsmax. */
+ break;
+ case 1156: /* stsmaxlb */
+ case 1085: /* ldsmaxlb */
+ value = 1085; /* --> ldsmaxlb. */
+ break;
+ case 1157: /* stsmaxlh */
+ case 1088: /* ldsmaxlh */
+ value = 1088; /* --> ldsmaxlh. */
+ break;
+ case 1158: /* stsmaxl */
+ case 1091: /* ldsmaxl */
+ value = 1091; /* --> ldsmaxl. */
+ break;
+ case 1159: /* stsminb */
+ case 1093: /* ldsminb */
+ value = 1093; /* --> ldsminb. */
+ break;
+ case 1160: /* stsminh */
+ case 1094: /* ldsminh */
+ value = 1094; /* --> ldsminh. */
+ break;
+ case 1161: /* stsmin */
+ case 1095: /* ldsmin */
+ value = 1095; /* --> ldsmin. */
+ break;
+ case 1162: /* stsminlb */
+ case 1097: /* ldsminlb */
+ value = 1097; /* --> ldsminlb. */
+ break;
+ case 1163: /* stsminlh */
+ case 1100: /* ldsminlh */
+ value = 1100; /* --> ldsminlh. */
+ break;
+ case 1164: /* stsminl */
+ case 1103: /* ldsminl */
+ value = 1103; /* --> ldsminl. */
+ break;
+ case 1165: /* stumaxb */
+ case 1105: /* ldumaxb */
+ value = 1105; /* --> ldumaxb. */
+ break;
+ case 1166: /* stumaxh */
+ case 1106: /* ldumaxh */
+ value = 1106; /* --> ldumaxh. */
+ break;
+ case 1167: /* stumax */
+ case 1107: /* ldumax */
+ value = 1107; /* --> ldumax. */
+ break;
+ case 1168: /* stumaxlb */
+ case 1109: /* ldumaxlb */
+ value = 1109; /* --> ldumaxlb. */
+ break;
+ case 1169: /* stumaxlh */
+ case 1112: /* ldumaxlh */
+ value = 1112; /* --> ldumaxlh. */
+ break;
+ case 1170: /* stumaxl */
+ case 1115: /* ldumaxl */
+ value = 1115; /* --> ldumaxl. */
+ break;
+ case 1171: /* stuminb */
+ case 1117: /* lduminb */
+ value = 1117; /* --> lduminb. */
+ break;
+ case 1172: /* stuminh */
+ case 1118: /* lduminh */
+ value = 1118; /* --> lduminh. */
+ break;
+ case 1173: /* stumin */
+ case 1119: /* ldumin */
+ value = 1119; /* --> ldumin. */
+ break;
+ case 1174: /* stuminlb */
+ case 1121: /* lduminlb */
+ value = 1121; /* --> lduminlb. */
+ break;
+ case 1175: /* stuminlh */
+ case 1124: /* lduminlh */
+ value = 1124; /* --> lduminlh. */
+ break;
+ case 1176: /* stuminl */
+ case 1127: /* lduminl */
+ value = 1127; /* --> lduminl. */
+ break;
+ case 1178: /* mov */
+ case 1177: /* movn */
+ value = 1177; /* --> movn. */
+ break;
+ case 1180: /* mov */
+ case 1179: /* movz */
+ value = 1179; /* --> movz. */
+ break;
+ case 1226: /* autibsp */
+ case 1225: /* autibz */
+ case 1224: /* autiasp */
+ case 1223: /* autiaz */
+ case 1222: /* pacibsp */
+ case 1221: /* pacibz */
+ case 1220: /* paciasp */
+ case 1219: /* paciaz */
+ case 1200: /* psb */
+ case 1199: /* esb */
+ case 1198: /* autib1716 */
+ case 1197: /* autia1716 */
+ case 1196: /* pacib1716 */
+ case 1195: /* pacia1716 */
+ case 1194: /* xpaclri */
+ case 1193: /* sevl */
+ case 1192: /* sev */
+ case 1191: /* wfi */
+ case 1190: /* wfe */
+ case 1189: /* yield */
+ case 1188: /* bti */
+ case 1187: /* csdb */
+ case 1186: /* nop */
+ case 1185: /* hint */
+ value = 1185; /* --> hint. */
+ break;
+ case 1204: /* pssbb */
+ case 1203: /* ssbb */
+ case 1202: /* dsb */
+ value = 1202; /* --> dsb. */
+ break;
+ case 1215: /* cpp */
+ case 1214: /* dvp */
+ case 1213: /* cfp */
+ case 1212: /* tlbi */
+ case 1211: /* ic */
+ case 1210: /* dc */
+ case 1209: /* at */
+ case 1208: /* sys */
+ value = 1208; /* --> sys. */
+ break;
+ case 2024: /* bic */
+ case 1274: /* and */
+ value = 1274; /* --> and. */
+ break;
+ case 1257: /* mov */
+ case 1276: /* and */
+ value = 1276; /* --> and. */
+ break;
+ case 1261: /* movs */
+ case 1277: /* ands */
+ value = 1277; /* --> ands. */
+ break;
+ case 2025: /* cmple */
+ case 1312: /* cmpge */
+ value = 1312; /* --> cmpge. */
+ break;
+ case 2028: /* cmplt */
+ case 1315: /* cmpgt */
+ value = 1315; /* --> cmpgt. */
+ break;
+ case 2026: /* cmplo */
+ case 1317: /* cmphi */
+ value = 1317; /* --> cmphi. */
+ break;
+ case 2027: /* cmpls */
+ case 1320: /* cmphs */
+ value = 1320; /* --> cmphs. */
+ break;
+ case 1254: /* mov */
+ case 1342: /* cpy */
+ value = 1342; /* --> cpy. */
+ break;
+ case 1256: /* mov */
+ case 1343: /* cpy */
+ value = 1343; /* --> cpy. */
+ break;
+ case 2035: /* fmov */
+ case 1259: /* mov */
+ case 1344: /* cpy */
+ value = 1344; /* --> cpy. */
break;
- case 1247: /* mov */
- case 1266: /* and */
- value = 1266; /* --> and. */
- break;
- case 1251: /* movs */
- case 1267: /* ands */
- value = 1267; /* --> ands. */
- break;
- case 2015: /* cmple */
- case 1302: /* cmpge */
- value = 1302; /* --> cmpge. */
- break;
- case 2018: /* cmplt */
- case 1305: /* cmpgt */
- value = 1305; /* --> cmpgt. */
- break;
- case 2016: /* cmplo */
- case 1307: /* cmphi */
- value = 1307; /* --> cmphi. */
- break;
- case 2017: /* cmpls */
- case 1310: /* cmphs */
- value = 1310; /* --> cmphs. */
- break;
- case 1244: /* mov */
- case 1332: /* cpy */
- value = 1332; /* --> cpy. */
- break;
- case 1246: /* mov */
- case 1333: /* cpy */
- value = 1333; /* --> cpy. */
- break;
- case 2025: /* fmov */
case 1249: /* mov */
- case 1334: /* cpy */
- value = 1334; /* --> cpy. */
+ case 1356: /* dup */
+ value = 1356; /* --> dup. */
break;
- case 1239: /* mov */
- case 1346: /* dup */
- value = 1346; /* --> dup. */
+ case 1251: /* mov */
+ case 1248: /* mov */
+ case 1357: /* dup */
+ value = 1357; /* --> dup. */
break;
- case 1241: /* mov */
- case 1238: /* mov */
- case 1347: /* dup */
- value = 1347; /* --> dup. */
+ case 2034: /* fmov */
+ case 1253: /* mov */
+ case 1358: /* dup */
+ value = 1358; /* --> dup. */
break;
- case 2024: /* fmov */
- case 1243: /* mov */
- case 1348: /* dup */
- value = 1348; /* --> dup. */
+ case 1252: /* mov */
+ case 1359: /* dupm */
+ value = 1359; /* --> dupm. */
break;
- case 1242: /* mov */
- case 1349: /* dupm */
- value = 1349; /* --> dupm. */
+ case 2029: /* eon */
+ case 1361: /* eor */
+ value = 1361; /* --> eor. */
break;
- case 2019: /* eon */
- case 1351: /* eor */
- value = 1351; /* --> eor. */
+ case 1262: /* not */
+ case 1363: /* eor */
+ value = 1363; /* --> eor. */
break;
- case 1252: /* not */
- case 1353: /* eor */
- value = 1353; /* --> eor. */
+ case 1263: /* nots */
+ case 1364: /* eors */
+ value = 1364; /* --> eors. */
break;
- case 1253: /* nots */
- case 1354: /* eors */
- value = 1354; /* --> eors. */
+ case 2030: /* facle */
+ case 1369: /* facge */
+ value = 1369; /* --> facge. */
break;
- case 2020: /* facle */
- case 1359: /* facge */
- value = 1359; /* --> facge. */
+ case 2031: /* faclt */
+ case 1370: /* facgt */
+ value = 1370; /* --> facgt. */
break;
- case 2021: /* faclt */
- case 1360: /* facgt */
- value = 1360; /* --> facgt. */
+ case 2032: /* fcmle */
+ case 1383: /* fcmge */
+ value = 1383; /* --> fcmge. */
break;
- case 2022: /* fcmle */
- case 1373: /* fcmge */
- value = 1373; /* --> fcmge. */
+ case 2033: /* fcmlt */
+ case 1385: /* fcmgt */
+ value = 1385; /* --> fcmgt. */
break;
- case 2023: /* fcmlt */
- case 1375: /* fcmgt */
- value = 1375; /* --> fcmgt. */
+ case 1246: /* fmov */
+ case 1391: /* fcpy */
+ value = 1391; /* --> fcpy. */
break;
- case 1236: /* fmov */
- case 1381: /* fcpy */
- value = 1381; /* --> fcpy. */
+ case 1245: /* fmov */
+ case 1414: /* fdup */
+ value = 1414; /* --> fdup. */
break;
- case 1235: /* fmov */
- case 1404: /* fdup */
- value = 1404; /* --> fdup. */
+ case 1247: /* mov */
+ case 1745: /* orr */
+ value = 1745; /* --> orr. */
break;
- case 1237: /* mov */
- case 1735: /* orr */
- value = 1735; /* --> orr. */
+ case 2036: /* orn */
+ case 1746: /* orr */
+ value = 1746; /* --> orr. */
break;
- case 2026: /* orn */
- case 1736: /* orr */
- value = 1736; /* --> orr. */
+ case 1250: /* mov */
+ case 1748: /* orr */
+ value = 1748; /* --> orr. */
break;
- case 1240: /* mov */
- case 1738: /* orr */
- value = 1738; /* --> orr. */
+ case 1260: /* movs */
+ case 1749: /* orrs */
+ value = 1749; /* --> orrs. */
break;
- case 1250: /* movs */
- case 1739: /* orrs */
- value = 1739; /* --> orrs. */
+ case 1255: /* mov */
+ case 1811: /* sel */
+ value = 1811; /* --> sel. */
break;
- case 1245: /* mov */
- case 1801: /* sel */
- value = 1801; /* --> sel. */
- break;
- case 1248: /* mov */
- case 1802: /* sel */
- value = 1802; /* --> sel. */
+ case 1258: /* mov */
+ case 1812: /* sel */
+ value = 1812; /* --> sel. */
break;
default: return NULL;
}
@@ -627,8 +627,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
- case 157:
- case 158:
case 159:
case 160:
case 161:
@@ -637,8 +635,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 164:
case 165:
case 166:
- case 179:
- case 180:
+ case 167:
+ case 168:
case 181:
case 182:
case 183:
@@ -646,8 +644,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 185:
case 186:
case 187:
- case 191:
- case 194:
+ case 188:
+ case 189:
+ case 193:
+ case 196:
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 196:
+ case 198:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -693,16 +693,16 @@ aarch64_insert_operand (const aarch64_operand *self,
case 79:
case 80:
case 81:
- case 154:
case 156:
- case 171:
- case 172:
+ case 158:
case 173:
case 174:
case 175:
case 176:
case 177:
case 178:
+ case 179:
+ case 180:
return aarch64_ins_imm (self, info, code, inst, errors);
case 42:
case 43:
@@ -712,10 +712,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 46:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 50:
- case 145:
+ case 147:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 67:
- case 152:
+ case 154:
return aarch64_ins_limm (self, info, code, inst, errors);
case 68:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -725,67 +725,67 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 72:
case 73:
- case 150:
+ case 152:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 74:
- case 149:
+ case 151:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 75:
case 76:
return aarch64_ins_cond (self, info, code, inst, errors);
case 82:
- case 89:
+ case 91:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 83:
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 84:
case 85:
case 86:
+ case 88:
+ case 90:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 87:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
- case 88:
+ case 89:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
- case 90:
- return aarch64_ins_addr_offset (self, info, code, inst, errors);
- case 91:
- return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 92:
- return aarch64_ins_sysreg (self, info, code, inst, errors);
+ return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 93:
- return aarch64_ins_pstatefield (self, info, code, inst, errors);
+ return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 94:
+ return aarch64_ins_sysreg (self, info, code, inst, errors);
case 95:
+ return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 96:
case 97:
case 98:
- return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 99:
case 100:
- return aarch64_ins_barrier (self, info, code, inst, errors);
+ return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 101:
- return aarch64_ins_prfop (self, info, code, inst, errors);
case 102:
+ return aarch64_ins_barrier (self, info, code, inst, errors);
case 103:
- return aarch64_ins_hint (self, info, code, inst, errors);
+ return aarch64_ins_prfop (self, info, code, inst, errors);
case 104:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 105:
+ return aarch64_ins_hint (self, info, code, inst, errors);
case 106:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 107:
case 108:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 109:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 110:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 111:
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 112:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 113:
case 114:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 115:
case 116:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 117:
case 118:
case 119:
@@ -797,57 +797,59 @@ aarch64_insert_operand (const aarch64_operand *self,
case 125:
case 126:
case 127:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 128:
case 129:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 130:
case 131:
case 132:
case 133:
case 134:
case 135:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 136:
case 137:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 138:
case 139:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 140:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 141:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 142:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 143:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 144:
- return aarch64_ins_sve_asimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ case 145:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 146:
+ return aarch64_ins_sve_asimm (self, info, code, inst, errors);
+ case 148:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
- case 147:
+ case 149:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
- case 148:
+ case 150:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 151:
- return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 153:
- return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
+ return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 155:
+ return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
+ case 157:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 167:
- case 168:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 169:
case 170:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
+ case 171:
+ case 172:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 188:
- case 189:
case 190:
- return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 191:
case 192:
+ return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 194:
return aarch64_ins_sve_index (self, info, code, inst, errors);
- case 193:
case 195:
+ case 197:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index fc7ac88..e53b98a 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -690,7 +690,8 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
insert_field (FLD_Rn, code, info->addr.base_regno, 0);
/* simm (imm9 or imm7) */
imm = info->addr.offset.imm;
- if (self->fields[0] == FLD_imm7)
+ if (self->fields[0] == FLD_imm7
+ || info->qualifier == AARCH64_OPND_QLF_imm_tag)
/* scaled immediate in ld/st pair instructions.. */
imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
insert_field (self->fields[0], code, imm, 0);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index cac71af..a2728d3 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -40,7 +40,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0xxx0000xxxxxxxxxxxxxxxxxxxxxxxx
adr. */
- return 1172;
+ return 1182;
}
else
{
@@ -48,7 +48,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1xxx0000xxxxxxxxxxxxxxxxxxxxxxxx
adrp. */
- return 1173;
+ return 1183;
}
}
else
@@ -115,7 +115,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x000xxxxx0xxxxxxxxxxxxxxx
stxrb. */
- return 927;
+ return 935;
}
else
{
@@ -123,7 +123,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x000xxxxx0xxxxxxxxxxxxxxx
stxrh. */
- return 933;
+ return 941;
}
}
else
@@ -132,7 +132,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x000xxxxx0xxxxxxxxxxxxxxx
stxr. */
- return 939;
+ return 947;
}
}
else
@@ -143,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x001xxxxx0xxxxxxxxxxxxxxx
casp. */
- return 1007;
+ return 1017;
}
else
{
@@ -151,7 +151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x001xxxxx0xxxxxxxxxxxxxxx
stxp. */
- return 941;
+ return 949;
}
}
}
@@ -167,7 +167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x000xxxxx1xxxxxxxxxxxxxxx
stlxrb. */
- return 928;
+ return 936;
}
else
{
@@ -175,7 +175,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x000xxxxx1xxxxxxxxxxxxxxx
stlxrh. */
- return 934;
+ return 942;
}
}
else
@@ -184,7 +184,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x000xxxxx1xxxxxxxxxxxxxxx
stlxr. */
- return 940;
+ return 948;
}
}
else
@@ -195,7 +195,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x001xxxxx1xxxxxxxxxxxxxxx
caspl. */
- return 1009;
+ return 1019;
}
else
{
@@ -203,18 +203,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x001xxxxx1xxxxxxxxxxxxxxx
stlxp. */
- return 942;
+ return 950;
}
}
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx10100x00xxxxxxxxxxxxxxxxxxxxxx
- stnp. */
- return 958;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x010100x00xxxxxxxxxxxxxxxxxxxxxx
+ stnp. */
+ return 966;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110100x00xxxxxxxxxxxxxxxxxxxxxx
+ stgp. */
+ return 975;
+ }
}
}
else
@@ -231,7 +242,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x100xxxxx0xxxxxxxxxxxxxxx
stllrb. */
- return 956;
+ return 964;
}
else
{
@@ -239,7 +250,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x100xxxxx0xxxxxxxxxxxxxxx
stllr. */
- return 955;
+ return 963;
}
}
else
@@ -252,7 +263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x101xxxxx0xxxxxxxxxxxxxxx
casb. */
- return 995;
+ return 1005;
}
else
{
@@ -260,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x101xxxxx0xxxxxxxxxxxxxxx
cash. */
- return 996;
+ return 1006;
}
}
else
@@ -269,7 +280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x101xxxxx0xxxxxxxxxxxxxxx
cas. */
- return 997;
+ return 1007;
}
}
}
@@ -285,7 +296,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x100xxxxx1xxxxxxxxxxxxxxx
stlrb. */
- return 931;
+ return 939;
}
else
{
@@ -293,7 +304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x100xxxxx1xxxxxxxxxxxxxxx
stlrh. */
- return 937;
+ return 945;
}
}
else
@@ -302,7 +313,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x100xxxxx1xxxxxxxxxxxxxxx
stlr. */
- return 947;
+ return 955;
}
}
else
@@ -315,7 +326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x101xxxxx1xxxxxxxxxxxxxxx
caslb. */
- return 999;
+ return 1009;
}
else
{
@@ -323,7 +334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x101xxxxx1xxxxxxxxxxxxxxx
caslh. */
- return 1002;
+ return 1012;
}
}
else
@@ -332,18 +343,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x101xxxxx1xxxxxxxxxxxxxxx
casl. */
- return 1005;
+ return 1015;
}
}
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx10100x10xxxxxxxxxxxxxxxxxxxxxx
- stp. */
- return 967;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x010100x10xxxxxxxxxxxxxxxxxxxxxx
+ stp. */
+ return 976;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110100x10xxxxxxxxxxxxxxxxxxxxxx
+ stgp. */
+ return 981;
+ }
}
}
}
@@ -365,7 +387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x010xxxxx0xxxxxxxxxxxxxxx
ldxrb. */
- return 929;
+ return 937;
}
else
{
@@ -373,7 +395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x010xxxxx0xxxxxxxxxxxxxxx
ldxrh. */
- return 935;
+ return 943;
}
}
else
@@ -382,7 +404,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x010xxxxx0xxxxxxxxxxxxxxx
ldxr. */
- return 943;
+ return 951;
}
}
else
@@ -393,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x011xxxxx0xxxxxxxxxxxxxxx
caspa. */
- return 1008;
+ return 1018;
}
else
{
@@ -401,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x011xxxxx0xxxxxxxxxxxxxxx
ldxp. */
- return 945;
+ return 953;
}
}
}
@@ -417,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x010xxxxx1xxxxxxxxxxxxxxx
ldaxrb. */
- return 930;
+ return 938;
}
else
{
@@ -425,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x010xxxxx1xxxxxxxxxxxxxxx
ldaxrh. */
- return 936;
+ return 944;
}
}
else
@@ -434,7 +456,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x010xxxxx1xxxxxxxxxxxxxxx
ldaxr. */
- return 944;
+ return 952;
}
}
else
@@ -445,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x011xxxxx1xxxxxxxxxxxxxxx
caspal. */
- return 1010;
+ return 1020;
}
else
{
@@ -453,7 +475,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x011xxxxx1xxxxxxxxxxxxxxx
ldaxp. */
- return 946;
+ return 954;
}
}
}
@@ -466,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010100x01xxxxxxxxxxxxxxxxxxxxxx
ldnp. */
- return 959;
+ return 967;
}
else
{
@@ -474,7 +496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110100x01xxxxxxxxxxxxxxxxxxxxxx
ldpsw. */
- return 966;
+ return 974;
}
}
}
@@ -494,7 +516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x110xxxxx0xxxxxxxxxxxxxxx
ldlarb. */
- return 953;
+ return 961;
}
else
{
@@ -502,7 +524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x110xxxxx0xxxxxxxxxxxxxxx
ldlarh. */
- return 954;
+ return 962;
}
}
else
@@ -511,7 +533,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x110xxxxx0xxxxxxxxxxxxxxx
ldlar. */
- return 952;
+ return 960;
}
}
else
@@ -524,7 +546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x111xxxxx0xxxxxxxxxxxxxxx
casab. */
- return 998;
+ return 1008;
}
else
{
@@ -532,7 +554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x111xxxxx0xxxxxxxxxxxxxxx
casah. */
- return 1001;
+ return 1011;
}
}
else
@@ -541,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x111xxxxx0xxxxxxxxxxxxxxx
casa. */
- return 1004;
+ return 1014;
}
}
}
@@ -557,7 +579,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x110xxxxx1xxxxxxxxxxxxxxx
ldarb. */
- return 932;
+ return 940;
}
else
{
@@ -565,7 +587,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x110xxxxx1xxxxxxxxxxxxxxx
ldarh. */
- return 938;
+ return 946;
}
}
else
@@ -574,7 +596,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x110xxxxx1xxxxxxxxxxxxxxx
ldar. */
- return 948;
+ return 956;
}
}
else
@@ -587,7 +609,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x111xxxxx1xxxxxxxxxxxxxxx
casalb. */
- return 1000;
+ return 1010;
}
else
{
@@ -595,7 +617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x111xxxxx1xxxxxxxxxxxxxxx
casalh. */
- return 1003;
+ return 1013;
}
}
else
@@ -604,7 +626,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x111xxxxx1xxxxxxxxxxxxxxx
casal. */
- return 1006;
+ return 1016;
}
}
}
@@ -617,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010100x11xxxxxxxxxxxxxxxxxxxxxx
ldp. */
- return 968;
+ return 977;
}
else
{
@@ -625,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110100x11xxxxxxxxxxxxxxxxxxxxxx
ldpsw. */
- return 971;
+ return 980;
}
}
}
@@ -643,7 +665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x011000xxxxxxxxxxxxxxxxxxxxxxxx
ldr. */
- return 972;
+ return 982;
}
else
{
@@ -653,7 +675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011000xxxxxxxxxxxxxxxxxxxxxxxx
ldrsw. */
- return 974;
+ return 984;
}
else
{
@@ -661,7 +683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
11011000xxxxxxxxxxxxxxxxxxxxxxxx
prfm. */
- return 975;
+ return 985;
}
}
}
@@ -685,7 +707,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000000xxxxxxxxx00xxxxxxxxxx
sturb. */
- return 913;
+ return 921;
}
else
{
@@ -693,7 +715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000000xxxxxxxxx00xxxxxxxxxx
sturh. */
- return 918;
+ return 926;
}
}
else
@@ -702,7 +724,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000000xxxxxxxxx00xxxxxxxxxx
stur. */
- return 921;
+ return 929;
}
}
else
@@ -715,7 +737,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000010xxxxxxxxx00xxxxxxxxxx
ldurb. */
- return 914;
+ return 922;
}
else
{
@@ -723,7 +745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000010xxxxxxxxx00xxxxxxxxxx
ldurh. */
- return 919;
+ return 927;
}
}
else
@@ -732,7 +754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000010xxxxxxxxx00xxxxxxxxxx
ldur. */
- return 922;
+ return 930;
}
}
}
@@ -746,7 +768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
001110001x0xxxxxxxxx00xxxxxxxxxx
ldursb. */
- return 915;
+ return 923;
}
else
{
@@ -754,7 +776,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101110001x0xxxxxxxxx00xxxxxxxxxx
ldursw. */
- return 923;
+ return 931;
}
}
else
@@ -765,7 +787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011110001x0xxxxxxxxx00xxxxxxxxxx
ldursh. */
- return 920;
+ return 928;
}
else
{
@@ -773,7 +795,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111110001x0xxxxxxxxx00xxxxxxxxxx
prfum. */
- return 924;
+ return 932;
}
}
}
@@ -800,7 +822,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxx000000xxxxxxxxxx
ldaddb. */
- return 1023;
+ return 1033;
}
else
{
@@ -808,7 +830,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxx000000xxxxxxxxxx
ldaddh. */
- return 1024;
+ return 1034;
}
}
else
@@ -817,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxx000000xxxxxxxxxx
ldadd. */
- return 1025;
+ return 1035;
}
}
else
@@ -830,7 +852,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxx000000xxxxxxxxxx
ldaddab. */
- return 1026;
+ return 1036;
}
else
{
@@ -838,7 +860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxx000000xxxxxxxxxx
ldaddah. */
- return 1029;
+ return 1039;
}
}
else
@@ -847,7 +869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxx000000xxxxxxxxxx
ldadda. */
- return 1032;
+ return 1042;
}
}
}
@@ -863,7 +885,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxx000000xxxxxxxxxx
ldaddlb. */
- return 1027;
+ return 1037;
}
else
{
@@ -871,7 +893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxx000000xxxxxxxxxx
ldaddlh. */
- return 1030;
+ return 1040;
}
}
else
@@ -880,7 +902,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxx000000xxxxxxxxxx
ldaddl. */
- return 1033;
+ return 1043;
}
}
else
@@ -893,7 +915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxx000000xxxxxxxxxx
ldaddalb. */
- return 1028;
+ return 1038;
}
else
{
@@ -901,7 +923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxx000000xxxxxxxxxx
ldaddalh. */
- return 1031;
+ return 1041;
}
}
else
@@ -910,7 +932,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxx000000xxxxxxxxxx
ldaddal. */
- return 1034;
+ return 1044;
}
}
}
@@ -929,7 +951,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxx100000xxxxxxxxxx
swpb. */
- return 1011;
+ return 1021;
}
else
{
@@ -937,7 +959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxx100000xxxxxxxxxx
swph. */
- return 1012;
+ return 1022;
}
}
else
@@ -946,7 +968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxx100000xxxxxxxxxx
swp. */
- return 1013;
+ return 1023;
}
}
else
@@ -959,7 +981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxx100000xxxxxxxxxx
swpab. */
- return 1014;
+ return 1024;
}
else
{
@@ -967,7 +989,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxx100000xxxxxxxxxx
swpah. */
- return 1017;
+ return 1027;
}
}
else
@@ -976,7 +998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxx100000xxxxxxxxxx
swpa. */
- return 1020;
+ return 1030;
}
}
}
@@ -992,7 +1014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxx100000xxxxxxxxxx
swplb. */
- return 1015;
+ return 1025;
}
else
{
@@ -1000,7 +1022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxx100000xxxxxxxxxx
swplh. */
- return 1018;
+ return 1028;
}
}
else
@@ -1009,7 +1031,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxx100000xxxxxxxxxx
swpl. */
- return 1021;
+ return 1031;
}
}
else
@@ -1022,7 +1044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxx100000xxxxxxxxxx
swpalb. */
- return 1016;
+ return 1026;
}
else
{
@@ -1030,7 +1052,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxx100000xxxxxxxxxx
swpalh. */
- return 1019;
+ return 1029;
}
}
else
@@ -1039,7 +1061,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxx100000xxxxxxxxxx
swpal. */
- return 1022;
+ return 1032;
}
}
}
@@ -1061,7 +1083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxx010000xxxxxxxxxx
ldsmaxb. */
- return 1071;
+ return 1081;
}
else
{
@@ -1069,7 +1091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxx010000xxxxxxxxxx
ldsmaxh. */
- return 1072;
+ return 1082;
}
}
else
@@ -1078,7 +1100,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxx010000xxxxxxxxxx
ldsmax. */
- return 1073;
+ return 1083;
}
}
else
@@ -1091,7 +1113,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxx010000xxxxxxxxxx
ldsmaxab. */
- return 1074;
+ return 1084;
}
else
{
@@ -1099,7 +1121,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxx010000xxxxxxxxxx
ldsmaxah. */
- return 1077;
+ return 1087;
}
}
else
@@ -1108,7 +1130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxx010000xxxxxxxxxx
ldsmaxa. */
- return 1080;
+ return 1090;
}
}
}
@@ -1124,7 +1146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxx010000xxxxxxxxxx
ldsmaxlb. */
- return 1075;
+ return 1085;
}
else
{
@@ -1132,7 +1154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011x[...]
[diff truncated at 100000 bytes]
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