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Re: setjmp on 32b MIPS with 64b FPRs

On Thu, 2013-08-22 at 12:50 +0300, Yossi Kreinin wrote:
> Hi,
> Apparently setjmp.S does not support 32b MIPS with 64b float registers
> - rather, the code has a path for 32b MIPS, which assumes 32b GPRs and
> FPRs, and a path for 64b MIPS, which assumes 64b GPRs and FPRs.
> However, there exist 32b MIPS processors where each $f register can
> keep a 64b double-precision number.
> The code below is based on setjmp.S and appears to work for me on 32b
> MIPS with 64b FPRs. It is not an actual patch that can be applied to
> setjmp.S because I'm unfamiliar with newlib and its build system and
> so I don't know which #ifdefs to use to detect which MIPS we're
> compiling for.
> Hope this helps,
> -- Yossi

Yossi,  Here is a patch with the proper ifdef's that should take care of
the problem.  It seems to work fine for me, could you test it too and if
it works for you and if someone approves it I can check it in.

Steve Ellcey

2013-08-23  Steve Ellcey  <>

	* libc/machine/mips/setjmp.S (FP_BYTES_PER_WORD): New.
	(FPOFF): Modify to use FP_BYTES_PER_WORD.

diff --git a/newlib/libc/machine/mips/setjmp.S
index 268cb18..0ebea59 100644
--- a/newlib/libc/machine/mips/setjmp.S
+++ b/newlib/libc/machine/mips/setjmp.S
@@ -42,20 +42,32 @@
 #ifdef __mips64
 #define BYTES_PER_WORD 8
+#define FP_BYTES_PER_WORD 8
 #define LOAD_GPR ld
-#define LOAD_FPR ldc1
 #define STORE_GPR sd
+#define LOAD_FPR ldc1
 #define STORE_FPR sdc1
 #define BYTES_PER_WORD 4
 #define LOAD_GPR lw
-#define LOAD_FPR lwc1
 #define STORE_GPR sw
+#ifdef __mips_fpr=64
+#define FP_BYTES_PER_WORD 8
+#define LOAD_FPR ldc1
+#define STORE_FPR sdc1
+#define FP_BYTES_PER_WORD 4
+#define LOAD_FPR lwc1
 #define STORE_FPR swc1
+/* Make sure we get the right alignment for FP regs.  */
+		        + FP_BYTES_PER_WORD - 1) \
 /* int setjmp (jmp_buf);  */
 	.globl	setjmp

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