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Re: [PATCH 18/28] powerpc: refactor powerpc64 lrint/lrintf/llrint/llrintf
- From: "Gabriel F. T. Gomes" <gabriel at inconstante dot eti dot br>
- To: Adhemerval Zanella <adhemerval dot zanella at linaro dot org>
- Cc: <libc-alpha at sourceware dot org>
- Date: Thu, 13 Jun 2019 16:30:05 -0300
- Subject: Re: [PATCH 18/28] powerpc: refactor powerpc64 lrint/lrintf/llrint/llrintf
- References: <20190329133529.22523-1-adhemerval.zanella@linaro.org> <20190329133529.22523-19-adhemerval.zanella@linaro.org>
Look good to me. Thanks
Reviewed-by: Gabriel F. T. Gomes <gabrielftg@linux.ibm.com>
On Fri, Mar 29 2019, Adhemerval Zanella wrote:
>
> The IFUNC support is also moved only to powerpc64 only, since for
> powerpc64le generic implementation resulting in optimized code.
Thanks for doing this.
For reference, here's the code that's generated on a powerpc64 build
targetting power4 (--with-cpu=power4 seems to be used on many distros):
000000000007e880 <.__llrint_power8>:
7e880: fc 20 0e 5c fctid f1,f1
7e884: 7c 23 00 66 mfvsrd r3,vs1
7e888: 4e 80 00 20 blr
000000000007e8a0 <.__llrint_power6x>:
7e8a0: fc 20 0e 5c fctid f1,f1
7e8a4: 7c 60 0d be mftgpr r3,f1
7e8a8: 4e 80 00 20 blr
000000000007e8c0 <.__llrint_ppc64>:
7e8c0: fc 20 0e 5c fctid f1,f1
7e8c4: d8 21 ff f8 stfd f1,-8(r1)
7e8c8: 60 00 00 00 nop
7e8cc: 60 00 00 00 nop
7e8d0: 60 00 00 00 nop
7e8d4: e8 61 ff f8 ld r3,-8(r1)
7e8d8: 4e 80 00 20 blr
powerpc64le doesn't suffer from this store-load scenario, since it is
only available for power8 and newer.