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Re: [PATCH] [powerpc] fegetmode: utilize faster method to get rounding mode
Adhemerval,
On 6/7/19 9:20 AM, Adhemerval Zanella wrote:
> On 06/06/2019 22:23, Paul A. Clarke wrote:
>> From: "Paul A. Clarke" <pc@us.ibm.com>
>> Add support to use 'mffsl' instruction if compiled for POWER9 (or later).
>
> What about using dl_hwcap to check for ISA 3.0 for fegetenv_register
> (as fesetenv_register does for fdp)? Not sure how performance-wise it would
> be, but in the other hand it would not require to build glibc using -mcpu=power9
> to actually use this instruction.
Good idea. I think I can do both, where the POWER9 instruction is used conditional
on hwcap2, and unconditionally if compiled with -mcpu=power9 (pseudocode, not actual
reviewable code, follows):
#ifdef _ARCH_PWR9
#define IS_ISA300() 1
#else
#define IS_ISA300() (hwcap2 & PPC_FEATURE2_ARCH_3_00)
#endif
rn = ({
union { double __d; unsigned long long __ll; } __u;
if (__builtin_expect(IS_ISA300(),1))
__asm__ volatile ("mffsl %0" : "=f" (__u.__d));
else
__u.__d = __builtin_mffs ();
__u.__ll & 0x0000000000000003LL;
});
PC