This is the mail archive of the
libc-alpha@sourceware.org
mailing list for the glibc project.
Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
- From: Joseph Myers <joseph at codesourcery dot com>
- To: Torvald Riegel <triegel at redhat dot com>
- Cc: Stefan Liebler <stli at linux dot vnet dot ibm dot com>, <libc-alpha at sourceware dot org>
- Date: Tue, 18 Apr 2017 21:17:22 +0000
- Subject: Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
- Authentication-results: sourceware.org; auth=none
- References: <1481905917-15654-1-git-send-email-stli@linux.vnet.ibm.com> <5857CF10.1060100@arm.com> <628f6311-239c-5eea-572c-c2acae6fcbee@linux.vnet.ibm.com> <1487017743.16322.80.camel@redhat.com> <60a34645-17e4-6693-1343-03c55b0c47ad@linux.vnet.ibm.com> <1487437038.20203.68.camel@redhat.com> <25ad863b-6f20-bfb7-95e6-3b04a2b3eee8@linux.vnet.ibm.com> <1487598702.20203.138.camel@redhat.com> <b57d3477-a041-7b06-82ac-6d2b6c6bb08c@linux.vnet.ibm.com> <1491487245.5374.161.camel@redhat.com>
On Thu, 6 Apr 2017, Torvald Riegel wrote:
> Have you been actually looking at these? The next line in the file is a
> pretty obvious hint that this is an LLSC machine, and atomic_exchange
> isn't defined anywhere:
>
> > /* Microblaze does not have byte and halfword forms of load and reserve and
> > diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
> > index 54c182b..3d9da0c 100644
> > --- a/sysdeps/mips/atomic-machine.h
> >
> > +++ b/sysdeps/mips/atomic-machine.h
> >
> > @@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
> > #define __HAVE_64B_ATOMICS 1
> > #endif
> >
> > +#define ATOMIC_EXCHANGE_USES_CAS 0
> >
> > +
>
> Please ask the MIPS maintainers to review this.
MIPS is an LLSC machine. However, XLP has a direct atomic exchange
instruction (so that will be used if _MIPS_ARCH_XLP is defined, in the
case where this header is using compiler builtins).
--
Joseph S. Myers
joseph@codesourcery.com