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Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
- From: Stefan Liebler <stli at linux dot vnet dot ibm dot com>
- To: libc-alpha at sourceware dot org
- Date: Wed, 19 Apr 2017 10:27:16 +0200
- Subject: Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
- Authentication-results: sourceware.org; auth=none
- References: <1481905917-15654-1-git-send-email-stli@linux.vnet.ibm.com> <5857CF10.1060100@arm.com> <628f6311-239c-5eea-572c-c2acae6fcbee@linux.vnet.ibm.com> <1487017743.16322.80.camel@redhat.com> <60a34645-17e4-6693-1343-03c55b0c47ad@linux.vnet.ibm.com> <1487437038.20203.68.camel@redhat.com> <25ad863b-6f20-bfb7-95e6-3b04a2b3eee8@linux.vnet.ibm.com> <1487598702.20203.138.camel@redhat.com> <b57d3477-a041-7b06-82ac-6d2b6c6bb08c@linux.vnet.ibm.com> <1491487245.5374.161.camel@redhat.com> <alpine.DEB.2.20.1704182112180.1253@digraph.polyomino.org.uk>
On 04/18/2017 11:17 PM, Joseph Myers wrote:
On Thu, 6 Apr 2017, Torvald Riegel wrote:
Have you been actually looking at these? The next line in the file is a
pretty obvious hint that this is an LLSC machine, and atomic_exchange
isn't defined anywhere:
/* Microblaze does not have byte and halfword forms of load and reserve and
diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
index 54c182b..3d9da0c 100644
--- a/sysdeps/mips/atomic-machine.h
+++ b/sysdeps/mips/atomic-machine.h
@@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#endif
+#define ATOMIC_EXCHANGE_USES_CAS 0
+
Please ask the MIPS maintainers to review this.
MIPS is an LLSC machine. However, XLP has a direct atomic exchange
instruction (so that will be used if _MIPS_ARCH_XLP is defined, in the
case where this header is using compiler builtins).
Thanks for review.
I've changed the patch to:
--- a/sysdeps/mips/atomic-machine.h
+++ b/sysdeps/mips/atomic-machine.h
@@ -92,7 +92,15 @@ typedef uintmax_t uatomic_max_t;
have no assembly alternative available and want to avoid the __sync_*
builtins if at all possible. */
-#define USE_ATOMIC_COMPILER_BUILTINS 1
+# define USE_ATOMIC_COMPILER_BUILTINS 1
+
+/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
+ instruction which will be used by __atomic_exchange_n. */
+# ifdef _MIPS_ARCH_XLP
+# define ATOMIC_EXCHANGE_USES_CAS 0
+# else
+# define ATOMIC_EXCHANGE_USES_CAS 1
+# endif
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
@@ -213,7 +221,8 @@ typedef uintmax_t uatomic_max_t;
/* This implementation using inline assembly will be removed once glibc
requires GCC 4.8 or later to build. */
-#define USE_ATOMIC_COMPILER_BUILTINS 0
+# define USE_ATOMIC_COMPILER_BUILTINS 0
+# define ATOMIC_EXCHANGE_USES_CAS 1
/* Compare and exchange. For all of the "xxx" routines, we expect a
"__prev" and a "__cmp" variable to be provided by the enclosing scope,