[PATCH] x86: support VMGEXIT

[Jan Beulich <jbeulich at suse dot com>]

It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.

gas/
2020-03-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (cpu_arch): Add .sev_es entry.
	* doc/c-i386.texi: Mention sev_es.
	* testsuite/gas/i386/arch-13.s: Add SEV-ES case.
	* testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
	expectations.
	* testsuite/gas/i386/arch-13-znver1.d,
	testsuite/gas/i386/arch-13-znver2.d: Extend -march=.

opcodes/
2020-03-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
	(prefix_table): Move vmmcall here. Add vmgexit.
	(rm_table): Replace vmmcall entry by prefix_table[] escape.
	* i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
	(cpu_flags): Add CpuSEV_ES entry.
	* i386-opc.h (CpuSEV_ES): New.
	(union i386_cpu_flags): Add cpusev_es field.
	* i386-opc.tbl (vmgexit): New.
	* i386-init.h, i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1167,6 +1167,8 @@ static const arch_entry cpu_arch[] =
     CPU_RDPRU_FLAGS, 0 },
   { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN,
     CPU_MCOMMIT_FLAGS, 0 },
+  { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN,
+    CPU_SEV_ES_FLAGS, 0 },
 };
 
 static const noarch_entry cpu_noarch[] =
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -251,6 +251,7 @@ accept various extension mnemonics.  For
 @code{cldemote},
 @code{rdpru},
 @code{mcommit},
+@code{sev_es},
 @code{lwp},
 @code{fma4},
 @code{xop},
@@ -1454,7 +1455,7 @@ supported on the CPU specified.  The cho
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
-@item @samp{.mcommit}
+@item @samp{.mcommit} @tab @samp{.sev_es}
 @end multitable
 
 Apart from the warning, there are only two other effects on
--- a/gas/testsuite/gas/i386/arch-13-znver1.d
+++ b/gas/testsuite/gas/i386/arch-13-znver1.d
@@ -1,5 +1,5 @@
 #source: arch-13.s
-#as: -march=znver1+rdpid+clwb+wbnoinvd+rdpru+mcommit
+#as: -march=znver1+rdpid+clwb+wbnoinvd+rdpru+mcommit+sev_es
 #objdump: -dw
 #name: i386 arch 13 (znver1)
 #dump: arch-13.d
--- a/gas/testsuite/gas/i386/arch-13-znver2.d
+++ b/gas/testsuite/gas/i386/arch-13-znver2.d
@@ -1,5 +1,5 @@
 #source: arch-13.s
-#as: -march=znver2
+#as: -march=znver2+sev_es
 #objdump: -dw
 #name: i386 arch 13 (znver2)
 #dump: arch-13.d
--- a/gas/testsuite/gas/i386/arch-13.d
+++ b/gas/testsuite/gas/i386/arch-13.d
@@ -1,4 +1,4 @@
-#as: -march=i686+smap+adx+rdseed+clzero+xsavec+xsaves+clflushopt+mwaitx+rdpid+clwb+wbnoinvd+rdpru+mcommit
+#as: -march=i686+smap+adx+rdseed+clzero+xsavec+xsaves+clflushopt+mwaitx+rdpid+clwb+wbnoinvd+rdpru+mcommit+sev_es
 #objdump: -dw
 #name: i386 arch 13
 
@@ -28,5 +28,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:[ 	]*f3 0f 01 fa[ 	]*mcommit[ 	]*
 [ 	]*[a-f0-9]+:[ 	]*f3 0f c7 f8[ 	]*rdpid  %eax
 [ 	]*[a-f0-9]+:[ 	]*0f 01 fd[ 	]*rdpru[ 	]*
+[ 	]*[a-f0-9]+:[ 	]*f3 0f 01 d9[ 	]*vmgexit[ 	]*
 [ 	]*[a-f0-9]+:[ 	]*f3 0f 09[ 	]*wbnoinvd[ 	]*
 #pass
--- a/gas/testsuite/gas/i386/arch-13.s
+++ b/gas/testsuite/gas/i386/arch-13.s
@@ -38,5 +38,8 @@
 # rdpru instruction
 	rdpru
 
+# vmgexit instruction
+	vmgexit
+
 # wbnoinvd instruction
 	wbnoinvd
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -959,6 +959,7 @@ enum
 enum
 {
   PREFIX_90 = 0,
+  PREFIX_0F01_REG_3_RM_1,
   PREFIX_0F01_REG_5_MOD_0,
   PREFIX_0F01_REG_5_MOD_3_RM_0,
   PREFIX_0F01_REG_5_MOD_3_RM_2,
@@ -3627,6 +3628,14 @@ static const struct dis386 prefix_table[
     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
   },
 
+  /* PREFIX_0F01_REG_3_MOD_1 */
+  {
+    { "vmmcall",	{ Skip_MODRM }, 0 },
+    { "vmgexit",	{ Skip_MODRM }, 0 },
+    { Bad_Opcode },
+    { "vmgexit",	{ Skip_MODRM }, 0 },
+  },
+
   /* PREFIX_0F01_REG_5_MOD_0 */
   {
     { Bad_Opcode },
@@ -11018,7 +11027,7 @@ static const struct dis386 rm_table[][8]
   {
     /* RM_0F01_REG_3 */
     { "vmrun",		{ Skip_MODRM }, 0 },
-    { "vmmcall",	{ Skip_MODRM }, 0 },
+    { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
     { "vmload",		{ Skip_MODRM }, 0 },
     { "vmsave",		{ Skip_MODRM }, 0 },
     { "stgi",		{ Skip_MODRM }, 0 },
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -309,6 +309,8 @@ static initializer cpu_flag_init[] =
     "CpuRDPRU" },
   { "CPU_MCOMMIT_FLAGS",
     "CpuMCOMMIT" },
+  { "CPU_SEV_ES_FLAGS",
+    "CpuSEV_ES" },
   { "CPU_ANY_X87_FLAGS",
     "CPU_ANY_287_FLAGS|Cpu8087" },
   { "CPU_ANY_287_FLAGS",
@@ -606,6 +608,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuENQCMD),
   BITFIELD (CpuRDPRU),
   BITFIELD (CpuMCOMMIT),
+  BITFIELD (CpuSEV_ES),
 #ifdef CpuUnused
   BITFIELD (CpuUnused),
 #endif
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -247,6 +247,8 @@ enum
   CpuRDPRU,
   /* MCOMMIT instruction required */
   CpuMCOMMIT,
+  /* SEV-ES instruction(s) required */
+  CpuSEV_ES,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -378,6 +380,7 @@ typedef union i386_cpu_flags
       unsigned int cpuenqcmd:1;
       unsigned int cpurdpru:1;
       unsigned int cpumcommit:1;
+      unsigned int cpusev_es:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2826,6 +2826,7 @@ invlpga, 2, 0xf01df, None, 3, CpuSVME, A
 skinit, 0, 0xf01de, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 skinit, 1, 0xf01de, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Dword }
 stgi, 0, 0xf01dc, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+vmgexit, 0, 0xf30f01d9, None, 3, CpuSEV_ES, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 vmload, 0, 0xf01da, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 vmload, 1, 0xf01da, None, 3, CpuSVME, AddrPrefixOpReg, { Acc|Word|Dword|Qword }
 vmmcall, 0, 0xf01d9, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }