Re: [PATCH] x86: fold certain VCVT{,U}SI2S{S,D} templates

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Fri, Feb 14, 2020 at 5:41 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> There don't really need to be separate Cpu64 and CpuNo64 templates for
> these. One small issue with this is that slightly strange code
>
>         .intel_syntax noprefix
>         .code16
>         .arch i286
>         .arch .avx
>         vcvtsi2sd xmm0, xmm0, dword ptr [bx]
>         vcvtsi2sd xmm0, xmm0, qword ptr [bx]
>
>         vcvtsi2sd xmm0, xmm0, ebx
>         vcvtsi2sd xmm0, xmm0, rbx
>
> now will match in behavior with the AVX512 counterparts in that not
> only the 2nd vcvtsi2sd won't assemble, but also the first. The last
> two, otoh, will continue to assemble fine (due to the lack of any
> memory operand size specifier). As a result, another way to make
> things behave more consistently would be to avoid the folding and
> add IgnoreSize to the CpuNo64 AVX512 variants. A 3rd way to do so
> would be to add Cpu386 to any such insn template.
>
> While doing this also make the usual cosmetic adjustments for the
> insns touched anyway. Additionally drop the redundant Cpu64 from
> the SAE forms of VCVT{,U}SI2SD - they won't assemble outside of
> 64-bit mode due to there not being anything to match the Reg64
> operand.
>
> opcodes/
> 2020-02-XX  Jan Beulich <jbeulich@suse.com>
>
>         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
>         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
>         VexW1 instead of open-coding them.
>         * i386-tbl.h: Re-generate.
>

OK.

Thanks.


-- 
H.J.