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[PATCH] Remove Intel syntax comments on movsx and movzx
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: binutils at sourceware dot org
- Date: Fri, 14 Feb 2020 05:45:57 -0800
- Subject: [PATCH] Remove Intel syntax comments on movsx and movzx
Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel
syntax comments on movsx and movzx to avoid confusing other readers.
* i386-opc.tbl (movsx): Remove Intel syntax comments.
(movzx): Likewise.
---
opcodes/ChangeLog | 5 +++++
opcodes/i386-opc.tbl | 5 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a53d646e42..103c508be0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl (movsx): Remove Intel syntax comments.
+ (movzx): Likewise.
+
2020-02-14 Jan Beulich <jbeulich@suse.com>
PR gas/25438
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 6eb7238589..01cf61a624 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -132,7 +132,6 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf
movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }
movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
-// Intel Syntax next 2 insns
movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
@@ -142,8 +141,8 @@ movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
// Move with zero extend.
movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
-// Intel Syntax next insn (the 64-bit variant is not particulary
-// useful since the zero extend 32->64 is implicit, but we can encode them).
+// The 64-bit variant is not particularly useful since the zero extend
+// 32->64 is implicit, but we can encode them.
movzx, 2, 0xfb6, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Push instructions.
--
2.24.1