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Re: [PATCH] RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive
- From: Jim Wilson <jimw at sifive dot com>
- To: Nelson Chu <nelson dot chu at sifive dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Tue, 12 Nov 2019 16:16:47 -0800
- Subject: Re: [PATCH] RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive
- References: <CAJYME4GQG4e+Y002pGZMeTMXgcKcOiUkJpzLbcY9fYq3di1uNw@mail.gmail.com>
On Mon, Nov 11, 2019 at 11:10 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> For the riscv assembler, if we use any floating point register (FPR),
> then the f-extension should be set. Currently we already have the
> similar check in the riscv_opcodes table, but the riscv_insn_types
> table, which is used to parse the ".insn" directive, have not yet. It
> would be good if the riscv_insn_types table has the same behavior as
> the riscv_opcodes table.
This looks good, and passes testing for the usual
riscv{32,64}-{elf,linux} targets. I committed it for you.
Jim