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[PATCH 06/13] x86: convert RegSIMD and RegMMX from bitfield to enumerator
- From: Jan Beulich <jbeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Wed, 30 Oct 2019 09:25:52 +0100
- Subject: [PATCH 06/13] x86: convert RegSIMD and RegMMX from bitfield to enumerator
- References: <773baa32-a12c-5da3-32a4-3db5a424d102@suse.com>
This is to further shrink the operand type representation.
gas/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size, operand_size_match,
operand_type_register_match, pi, check_VecOperands, match_template,
check_byte_reg, check_long_reg, check_qword_reg, process_operands,
build_modrm_byte, parse_real_register): Use "class" instead of
"regsimd" / "regmmx" fields.
opcodes/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
OPERAND_TYPE_REGZMM entries.
(operand_classes): Add RegMMX and RegSIMD entries.
(operand_types): Drop RegMMX and RegSIMD entries.
* i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
(RegMMX, RegSIMD): Delete.
(union i386_operand_type): Remove regmmx and regsimd fields.
* i386-opc.tbl (RegMMX): Define.
(RegXMM, RegYMM, RegZMM): Add Class=.
* i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
Class=RegSIMD.
* i386-init.h, i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2028,7 +2028,7 @@ match_mem_size (const insn_template *t,
operands at the same time, some special casing is needed
here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
down-conversion vpmov*. */
- || ((t->operand_types[wanted].bitfield.regsimd
+ || ((t->operand_types[wanted].bitfield.class == RegSIMD
&& !t->opcode_modifier.broadcast
&& (t->operand_types[wanted].bitfield.byte
|| t->operand_types[wanted].bitfield.word
@@ -2063,7 +2063,8 @@ operand_size_match (const insn_template
/* Check memory and accumulator operand size. */
for (j = 0; j < i.operands; j++)
{
- if (i.types[j].bitfield.class != Reg && !i.types[j].bitfield.regsimd
+ if (i.types[j].bitfield.class != Reg
+ && i.types[j].bitfield.class != RegSIMD
&& t->operand_types[j].bitfield.anysize)
continue;
@@ -2074,7 +2075,7 @@ operand_size_match (const insn_template
break;
}
- if (t->operand_types[j].bitfield.regsimd
+ if (t->operand_types[j].bitfield.class == RegSIMD
&& !match_simd_size (t, j, j))
{
match = 0;
@@ -2114,7 +2115,7 @@ mismatch:
&& !match_operand_size (t, j, given))
goto mismatch;
- if (t->operand_types[j].bitfield.regsimd
+ if (t->operand_types[j].bitfield.class == RegSIMD
&& !match_simd_size (t, j, given))
goto mismatch;
@@ -2171,17 +2172,17 @@ operand_type_register_match (i386_operan
i386_operand_type t1)
{
if (g0.bitfield.class != Reg
- && !g0.bitfield.regsimd
+ && g0.bitfield.class != RegSIMD
&& (!operand_type_check (g0, anymem)
|| g0.bitfield.unspecified
- || !t0.bitfield.regsimd))
+ || t0.bitfield.class != RegSIMD))
return 1;
if (g1.bitfield.class != Reg
- && !g1.bitfield.regsimd
+ && g1.bitfield.class != RegSIMD
&& (!operand_type_check (g1, anymem)
|| g1.bitfield.unspecified
- || !t1.bitfield.regsimd))
+ || t1.bitfield.class != RegSIMD))
return 1;
if (g0.bitfield.byte == g1.bitfield.byte
@@ -3045,8 +3046,8 @@ pi (const char *line, i386_insn *x)
pt (x->types[j]);
fprintf (stdout, "\n");
if (x->types[j].bitfield.class == Reg
- || x->types[j].bitfield.regmmx
- || x->types[j].bitfield.regsimd
+ || x->types[j].bitfield.class == RegMMX
+ || x->types[j].bitfield.class == RegSIMD
|| x->types[j].bitfield.class == SReg
|| x->types[j].bitfield.class == RegCR
|| x->types[j].bitfield.class == RegDR
@@ -5363,10 +5364,10 @@ check_VecOperands (const insn_template *
gas_assert (i.reg_operands == 2 || i.mask);
if (i.reg_operands == 2 && !i.mask)
{
- gas_assert (i.types[0].bitfield.regsimd);
+ gas_assert (i.types[0].bitfield.class == RegSIMD);
gas_assert (i.types[0].bitfield.xmmword
|| i.types[0].bitfield.ymmword);
- gas_assert (i.types[2].bitfield.regsimd);
+ gas_assert (i.types[2].bitfield.class == RegSIMD);
gas_assert (i.types[2].bitfield.xmmword
|| i.types[2].bitfield.ymmword);
if (operand_check == check_none)
@@ -5387,7 +5388,7 @@ check_VecOperands (const insn_template *
}
else if (i.reg_operands == 1 && i.mask)
{
- if (i.types[1].bitfield.regsimd
+ if (i.types[1].bitfield.class == RegSIMD
&& (i.types[1].bitfield.xmmword
|| i.types[1].bitfield.ymmword
|| i.types[1].bitfield.zmmword)
@@ -5578,7 +5579,7 @@ check_VecOperands (const insn_template *
else if (!i.types[op].bitfield.unspecified)
type = &i.types[op];
}
- else if (i.types[op].bitfield.regsimd
+ else if (i.types[op].bitfield.class == RegSIMD
&& t->opcode_modifier.evex != EVEXLIG)
{
if (i.types[op].bitfield.zmmword)
@@ -5784,10 +5785,10 @@ match_template (char mnem_suffix)
&& !t->opcode_modifier.broadcast
&& !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2)
- && ((!operand_types[0].bitfield.regmmx
- && !operand_types[0].bitfield.regsimd)
- || (!operand_types[t->operands > 1].bitfield.regmmx
- && !operand_types[t->operands > 1].bitfield.regsimd))
+ && ((operand_types[0].bitfield.class != RegMMX
+ && operand_types[0].bitfield.class != RegSIMD)
+ || (operand_types[t->operands > 1].bitfield.class != RegMMX
+ && operand_types[t->operands > 1].bitfield.class != RegSIMD))
&& (t->base_opcode != 0x0fc7
|| t->extension_opcode != 1 /* cmpxchg8b */))
continue;
@@ -5799,10 +5800,11 @@ match_template (char mnem_suffix)
? (!t->opcode_modifier.ignoresize
&& !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2)
- && ((!operand_types[0].bitfield.regmmx
- && !operand_types[0].bitfield.regsimd)
- || (!operand_types[t->operands > 1].bitfield.regmmx
- && !operand_types[t->operands > 1].bitfield.regsimd)))
+ && ((operand_types[0].bitfield.class != RegMMX
+ && operand_types[0].bitfield.class != RegSIMD)
+ || (operand_types[t->operands > 1].bitfield.class != RegMMX
+ && operand_types[t->operands > 1].bitfield.class
+ != RegSIMD)))
continue;
/* Do not verify operands when there are none. */
@@ -5978,8 +5980,8 @@ check_reverse:
found_reverse_match = Opcode_FloatD;
else if (operand_types[0].bitfield.xmmword
|| operand_types[i.operands - 1].bitfield.xmmword
- || operand_types[0].bitfield.regmmx
- || operand_types[i.operands - 1].bitfield.regmmx
+ || operand_types[0].bitfield.class == RegMMX
+ || operand_types[i.operands - 1].bitfield.class == RegMMX
|| is_any_vex_encoding(t))
found_reverse_match = (t->base_opcode & 0xee) != 0x6e
? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
@@ -6689,8 +6691,8 @@ check_byte_reg (void)
}
/* Any other register is bad. */
if (i.types[op].bitfield.class == Reg
- || i.types[op].bitfield.regmmx
- || i.types[op].bitfield.regsimd
+ || i.types[op].bitfield.class == RegMMX
+ || i.types[op].bitfield.class == RegSIMD
|| i.types[op].bitfield.class == SReg
|| i.types[op].bitfield.class == RegCR
|| i.types[op].bitfield.class == RegDR
@@ -6762,7 +6764,7 @@ check_long_reg (void)
{
if (intel_syntax
&& i.tm.opcode_modifier.toqword
- && !i.types[0].bitfield.regsimd)
+ && i.types[0].bitfield.class != RegSIMD)
{
/* Convert to QWORD. We want REX byte. */
i.suffix = QWORD_MNEM_SUFFIX;
@@ -6813,7 +6815,7 @@ check_qword_reg (void)
lowering is more complicated. */
if (intel_syntax
&& i.tm.opcode_modifier.todword
- && !i.types[0].bitfield.regsimd)
+ && i.types[0].bitfield.class != RegSIMD)
{
/* Convert to DWORD. We don't want REX byte. */
i.suffix = LONG_MNEM_SUFFIX;
@@ -6990,7 +6992,7 @@ process_operands (void)
/* Keep xmm0 for instructions with VEX prefix and 3
sources. */
i.tm.operand_types[0].bitfield.acc = 0;
- i.tm.operand_types[0].bitfield.regsimd = 1;
+ i.tm.operand_types[0].bitfield.class = RegSIMD;
goto duplicate;
}
else
@@ -7080,7 +7082,7 @@ duplicate:
unsigned int regnum, first_reg_in_group, last_reg_in_group;
/* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
- gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
+ gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
regnum = register_number (i.op[1].regs);
first_reg_in_group = regnum & ~3;
last_reg_in_group = first_reg_in_group + 3;
@@ -7225,7 +7227,7 @@ build_modrm_byte (void)
|| (i.reg_operands == 3 && i.mem_operands == 1))
&& i.tm.opcode_modifier.vexvvvv == VEXXDS
&& i.tm.opcode_modifier.vexw
- && i.tm.operand_types[dest].bitfield.regsimd);
+ && i.tm.operand_types[dest].bitfield.class == RegSIMD);
/* If VexW1 is set, the first non-immediate operand is the source and
the second non-immediate one is encoded in the immediate operand. */
@@ -7249,7 +7251,7 @@ build_modrm_byte (void)
i.types[i.operands] = imm8;
i.operands++;
- gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
+ gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
exp->X_op = O_constant;
exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
@@ -7263,13 +7265,13 @@ build_modrm_byte (void)
/* Turn on Imm8 again so that output_imm will generate it. */
i.types[0].bitfield.imm8 = 1;
- gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
+ gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
i.op[0].imms->X_add_number
|= register_number (i.op[reg_slot].regs) << 4;
gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
}
- gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
+ gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
i.vex.register_specifier = i.op[nds].regs;
}
else
@@ -7391,7 +7393,7 @@ build_modrm_byte (void)
if ((dest + 1) >= i.operands
|| ((op.bitfield.class != Reg
|| (!op.bitfield.dword && !op.bitfield.qword))
- && !op.bitfield.regsimd
+ && op.bitfield.class != RegSIMD
&& !operand_type_equal (&op, ®mask)))
abort ();
i.vex.register_specifier = i.op[vvvv].regs;
@@ -7411,11 +7413,11 @@ build_modrm_byte (void)
{
i.rm.reg = i.op[dest].regs->reg_num;
i.rm.regmem = i.op[source].regs->reg_num;
- if (i.op[dest].regs->reg_type.bitfield.regmmx
- || i.op[source].regs->reg_type.bitfield.regmmx)
+ if (i.op[dest].regs->reg_type.bitfield.class == RegMMX
+ || i.op[source].regs->reg_type.bitfield.class == RegMMX)
i.has_regmmx = TRUE;
- else if (i.op[dest].regs->reg_type.bitfield.regsimd
- || i.op[source].regs->reg_type.bitfield.regsimd)
+ else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD
+ || i.op[source].regs->reg_type.bitfield.class == RegSIMD)
{
if (i.types[dest].bitfield.zmmword
|| i.types[source].bitfield.zmmword)
@@ -7774,7 +7776,7 @@ build_modrm_byte (void)
|| i.types[op].bitfield.class == RegDR
|| i.types[op].bitfield.class == RegTR)
break;
- if (i.types[op].bitfield.regsimd)
+ if (i.types[op].bitfield.class == RegSIMD)
{
if (i.types[op].bitfield.zmmword)
i.has_regzmm = TRUE;
@@ -7784,7 +7786,7 @@ build_modrm_byte (void)
i.has_regxmm = TRUE;
break;
}
- if (i.types[op].bitfield.regmmx)
+ if (i.types[op].bitfield.class == RegMMX)
{
i.has_regmmx = TRUE;
break;
@@ -7850,7 +7852,7 @@ build_modrm_byte (void)
if ((type->bitfield.class != Reg
|| (!type->bitfield.dword && !type->bitfield.qword))
- && !type->bitfield.regsimd
+ && type->bitfield.class != RegSIMD
&& !operand_type_equal (type, ®mask))
abort ();
@@ -11015,7 +11017,7 @@ parse_real_register (char *reg_string, c
&& !cpu_arch_flags.bitfield.cpui386)
return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
+ if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
return (const reg_entry *) NULL;
if (!cpu_arch_flags.bitfield.cpuavx512f)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -436,13 +436,13 @@ static initializer operand_type_init[] =
{ "OPERAND_TYPE_JUMPABSOLUTE",
"JumpAbsolute" },
{ "OPERAND_TYPE_REGMMX",
- "RegMMX" },
+ "Class=RegMMX" },
{ "OPERAND_TYPE_REGXMM",
- "RegSIMD|Xmmword" },
+ "Class=RegSIMD|Xmmword" },
{ "OPERAND_TYPE_REGYMM",
- "RegSIMD|Ymmword" },
+ "Class=RegSIMD|Ymmword" },
{ "OPERAND_TYPE_REGZMM",
- "RegSIMD|Zmmword" },
+ "Class=RegSIMD|Zmmword" },
{ "OPERAND_TYPE_REGMASK",
"RegMask" },
{ "OPERAND_TYPE_ESSEG",
@@ -680,14 +680,14 @@ static const struct {
CLASS (RegCR),
CLASS (RegDR),
CLASS (RegTR),
+ CLASS (RegMMX),
+ CLASS (RegSIMD),
};
#undef CLASS
static bitfield operand_types[] =
{
- BITFIELD (RegMMX),
- BITFIELD (RegSIMD),
BITFIELD (RegMask),
BITFIELD (Imm1),
BITFIELD (Imm8),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -704,6 +704,8 @@ enum operand_class
RegCR, /* Control register */
RegDR, /* Debug register */
RegTR, /* Test register */
+ RegMMX, /* MMX register */
+ RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
};
/* Position of operand_type bits. */
@@ -712,10 +714,6 @@ enum
{
/* Class */
Class = CLASS_WIDTH - 1,
- /* MMX register */
- RegMMX,
- /* Vector registers */
- RegSIMD,
/* Vector Mask registers */
RegMask,
/* 1 bit immediate */
@@ -805,8 +803,6 @@ typedef union i386_operand_type
struct
{
unsigned int class:CLASS_WIDTH;
- unsigned int regmmx:1;
- unsigned int regsimd:1;
unsigned int regmask:1;
unsigned int imm1:1;
unsigned int imm8:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -36,9 +36,10 @@
#define Debug Class=RegDR
#define Test Class=RegTR
-#define RegXMM RegSIMD|Xmmword
-#define RegYMM RegSIMD|Ymmword
-#define RegZMM RegSIMD|Zmmword
+#define RegMMX Class=RegMMX
+#define RegXMM Class=RegSIMD|Xmmword
+#define RegYMM Class=RegSIMD|Ymmword
+#define RegZMM Class=RegSIMD|Zmmword
#define Size16 Size=SIZE16
#define Size32 Size=SIZE32
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -172,112 +172,112 @@ tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inv
tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
// MMX and simd registers.
-mm0, RegMMX, 0, 0, 29, 41
-mm1, RegMMX, 0, 1, 30, 42
-mm2, RegMMX, 0, 2, 31, 43
-mm3, RegMMX, 0, 3, 32, 44
-mm4, RegMMX, 0, 4, 33, 45
-mm5, RegMMX, 0, 5, 34, 46
-mm6, RegMMX, 0, 6, 35, 47
-mm7, RegMMX, 0, 7, 36, 48
-xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17
-xmm1, RegSIMD|Xmmword, 0, 1, 22, 18
-xmm2, RegSIMD|Xmmword, 0, 2, 23, 19
-xmm3, RegSIMD|Xmmword, 0, 3, 24, 20
-xmm4, RegSIMD|Xmmword, 0, 4, 25, 21
-xmm5, RegSIMD|Xmmword, 0, 5, 26, 22
-xmm6, RegSIMD|Xmmword, 0, 6, 27, 23
-xmm7, RegSIMD|Xmmword, 0, 7, 28, 24
-xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
-xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
-xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
-xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
-xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
-xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
-xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
-xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
-xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
-xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
-xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
-xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
-xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
-xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
-xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
-xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
-xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
-xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
-xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
-xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
-xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
-xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
-xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
-xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
+mm0, Class=RegMMX, 0, 0, 29, 41
+mm1, Class=RegMMX, 0, 1, 30, 42
+mm2, Class=RegMMX, 0, 2, 31, 43
+mm3, Class=RegMMX, 0, 3, 32, 44
+mm4, Class=RegMMX, 0, 4, 33, 45
+mm5, Class=RegMMX, 0, 5, 34, 46
+mm6, Class=RegMMX, 0, 6, 35, 47
+mm7, Class=RegMMX, 0, 7, 36, 48
+xmm0, Class=RegSIMD|Acc|Xmmword, 0, 0, 21, 17
+xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
+xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
+xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
+xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
+xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
+xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
+xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
+xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
+xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
+xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
+xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
+xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
+xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
+xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
+xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
+xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
+xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
+xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
+xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
+xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
+xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
+xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
+xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
+xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
+xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
+xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
+xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
+xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
+xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
+xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
+xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
// AVX registers.
-ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
-ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
-ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
-ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
-ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
-ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
-ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
-ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
-ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
-ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
-ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
-ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
-ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
-ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
-ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
-ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
-ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
-ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
-ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
-ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
-ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
-ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
-ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
-ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
-ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
-ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
-ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
-ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
-ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
-ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
-ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
-ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
+ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
+ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
+ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
+ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
+ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
+ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
+ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
+ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
+ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
+ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
+ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
+ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
+ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
+ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
+ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
+ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
+ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
// AVX512 registers.
-zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
-zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
-zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
-zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
-zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
-zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
-zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
-zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
-zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
-zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
-zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
-zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
-zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
-zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
-zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
-zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
-zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
-zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
-zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
-zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
-zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
-zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
-zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
-zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
-zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
-zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
-zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
-zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
-zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
-zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
-zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
-zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
+zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
+zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
+zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
+zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
+zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
+zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
+zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
+zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
+zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
+zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
+zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
+zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
+zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
+zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
+zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
+zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
+zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
+zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
+zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
+zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
+zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
+zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
+zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
+zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
// Bound registers for MPX
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval