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[PATCH 05/13] x86: convert Control/Debug/Test from bitfield to enumerator
- From: Jan Beulich <jbeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Wed, 30 Oct 2019 09:25:31 +0100
- Subject: [PATCH 05/13] x86: convert Control/Debug/Test from bitfield to enumerator
- References: <773baa32-a12c-5da3-32a4-3db5a424d102@suse.com>
This is to further shrink the operand type representation.
gas/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pi, check_byte_reg, build_modrm_byte,
parse_real_register): Use "class" instead of "control"/"debug"/
"test" fields.
opcodes/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
entries.
(operand_classes): Add RegCR, RegDR, and RegTR entries.
(operand_types): Drop Control, Debug, and Test entries.
* i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
(Control, Debug, Test): Delete.
(union i386_operand_type): Remove control, debug, and test
fields.
* i386-opc.tbl (Control, Debug, Test): Define.
* i386-reg.tbl: Replace Control by Class=RegCR, Debug by
Class=RegDR, and Test by Class=RegTR.
* i386-init.h, i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3048,9 +3048,9 @@ pi (const char *line, i386_insn *x)
|| x->types[j].bitfield.regmmx
|| x->types[j].bitfield.regsimd
|| x->types[j].bitfield.class == SReg
- || x->types[j].bitfield.control
- || x->types[j].bitfield.debug
- || x->types[j].bitfield.test)
+ || x->types[j].bitfield.class == RegCR
+ || x->types[j].bitfield.class == RegDR
+ || x->types[j].bitfield.class == RegTR)
fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
if (operand_type_check (x->types[j], imm))
pe (x->op[j].imms);
@@ -6692,9 +6692,9 @@ check_byte_reg (void)
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regsimd
|| i.types[op].bitfield.class == SReg
- || i.types[op].bitfield.control
- || i.types[op].bitfield.debug
- || i.types[op].bitfield.test)
+ || i.types[op].bitfield.class == RegCR
+ || i.types[op].bitfield.class == RegDR
+ || i.types[op].bitfield.class == RegTR)
{
as_bad (_("`%s%s' not allowed with `%s%c'"),
register_prefix,
@@ -7450,7 +7450,7 @@ build_modrm_byte (void)
}
if (flag_code != CODE_64BIT && (i.rex & REX_R))
{
- if (!i.types[!i.tm.opcode_modifier.regmem].bitfield.control)
+ if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
abort ();
i.rex &= ~REX_R;
add_prefix (LOCK_PREFIX_OPCODE);
@@ -7770,9 +7770,9 @@ build_modrm_byte (void)
|| i.types[op].bitfield.regbnd
|| i.types[op].bitfield.regmask
|| i.types[op].bitfield.class == SReg
- || i.types[op].bitfield.control
- || i.types[op].bitfield.debug
- || i.types[op].bitfield.test)
+ || i.types[op].bitfield.class == RegCR
+ || i.types[op].bitfield.class == RegDR
+ || i.types[op].bitfield.class == RegTR)
break;
if (i.types[op].bitfield.regsimd)
{
@@ -11009,9 +11009,9 @@ parse_real_register (char *reg_string, c
if ((r->reg_type.bitfield.dword
|| (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
- || r->reg_type.bitfield.control
- || r->reg_type.bitfield.debug
- || r->reg_type.bitfield.test)
+ || r->reg_type.bitfield.class == RegCR
+ || r->reg_type.bitfield.class == RegDR
+ || r->reg_type.bitfield.class == RegTR)
&& !cpu_arch_flags.bitfield.cpui386)
return (const reg_entry *) NULL;
@@ -11052,7 +11052,7 @@ parse_real_register (char *reg_string, c
}
if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
- && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
+ && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
&& flag_code != CODE_64BIT)
return (const reg_entry *) NULL;
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -422,11 +422,11 @@ static initializer operand_type_init[] =
{ "OPERAND_TYPE_SHIFTCOUNT",
"ShiftCount" },
{ "OPERAND_TYPE_CONTROL",
- "Control" },
+ "Class=RegCR" },
{ "OPERAND_TYPE_TEST",
- "Test" },
+ "Class=RegTR" },
{ "OPERAND_TYPE_DEBUG",
- "Debug" },
+ "Class=RegDR" },
{ "OPERAND_TYPE_FLOATREG",
"Class=Reg|Tbyte" },
{ "OPERAND_TYPE_FLOATACC",
@@ -677,6 +677,9 @@ static const struct {
} operand_classes[] = {
CLASS (Reg),
CLASS (SReg),
+ CLASS (RegCR),
+ CLASS (RegDR),
+ CLASS (RegTR),
};
#undef CLASS
@@ -701,9 +704,6 @@ static bitfield operand_types[] =
BITFIELD (Disp64),
BITFIELD (InOutPortReg),
BITFIELD (ShiftCount),
- BITFIELD (Control),
- BITFIELD (Debug),
- BITFIELD (Test),
BITFIELD (Acc),
BITFIELD (JumpAbsolute),
BITFIELD (EsSeg),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -701,6 +701,9 @@ enum operand_class
ClassNone,
Reg, /* GPRs and FP regs, distinguished by operand size */
SReg, /* Segment register */
+ RegCR, /* Control register */
+ RegDR, /* Debug register */
+ RegTR, /* Test register */
};
/* Position of operand_type bits. */
@@ -715,12 +718,6 @@ enum
RegSIMD,
/* Vector Mask registers */
RegMask,
- /* Control register */
- Control,
- /* Debug register */
- Debug,
- /* Test register */
- Test,
/* 1 bit immediate */
Imm1,
/* 8 bit immediate */
@@ -811,9 +808,6 @@ typedef union i386_operand_type
unsigned int regmmx:1;
unsigned int regsimd:1;
unsigned int regmask:1;
- unsigned int control:1;
- unsigned int debug:1;
- unsigned int test:1;
unsigned int imm1:1;
unsigned int imm8:1;
unsigned int imm8s:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -32,6 +32,10 @@
#define SReg Class=SReg
+#define Control Class=RegCR
+#define Debug Class=RegDR
+#define Test Class=RegTR
+
#define RegXMM RegSIMD|Xmmword
#define RegYMM RegSIMD|Ymmword
#define RegZMM RegSIMD|Zmmword
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -113,64 +113,64 @@ fs, Class=SReg, 0, 4, 44, 54
gs, Class=SReg, 0, 5, 45, 55
flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
// Control registers.
-cr0, Control, 0, 0, Dw2Inval, Dw2Inval
-cr1, Control, 0, 1, Dw2Inval, Dw2Inval
-cr2, Control, 0, 2, Dw2Inval, Dw2Inval
-cr3, Control, 0, 3, Dw2Inval, Dw2Inval
-cr4, Control, 0, 4, Dw2Inval, Dw2Inval
-cr5, Control, 0, 5, Dw2Inval, Dw2Inval
-cr6, Control, 0, 6, Dw2Inval, Dw2Inval
-cr7, Control, 0, 7, Dw2Inval, Dw2Inval
-cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
-cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
-cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
-cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
-cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
-cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
-cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
-cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
+cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
+cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
+cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
+cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
+cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
+cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
+cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
+cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
+cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
+cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
+cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
+cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
+cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
+cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
+cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
+cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
// Debug registers.
-db0, Debug, 0, 0, Dw2Inval, Dw2Inval
-db1, Debug, 0, 1, Dw2Inval, Dw2Inval
-db2, Debug, 0, 2, Dw2Inval, Dw2Inval
-db3, Debug, 0, 3, Dw2Inval, Dw2Inval
-db4, Debug, 0, 4, Dw2Inval, Dw2Inval
-db5, Debug, 0, 5, Dw2Inval, Dw2Inval
-db6, Debug, 0, 6, Dw2Inval, Dw2Inval
-db7, Debug, 0, 7, Dw2Inval, Dw2Inval
-db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
-db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
-db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
-db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
-db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
-db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
-db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
-db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
-dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
-dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
-dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
-dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
-dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
-dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
-dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
-dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
-dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
-dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
-dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
-dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
-dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
-dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
-dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
-dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
+db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
+db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
+db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
+db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
+db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
+db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
+db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
+db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
+db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
+db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
+db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
+db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
+db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
+db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
+db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
+db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
+dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
+dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
+dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
+dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
+dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
+dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
+dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
+dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
+dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
+dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
+dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
+dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
+dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
+dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
+dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
+dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
// Test registers.
-tr0, Test, 0, 0, Dw2Inval, Dw2Inval
-tr1, Test, 0, 1, Dw2Inval, Dw2Inval
-tr2, Test, 0, 2, Dw2Inval, Dw2Inval
-tr3, Test, 0, 3, Dw2Inval, Dw2Inval
-tr4, Test, 0, 4, Dw2Inval, Dw2Inval
-tr5, Test, 0, 5, Dw2Inval, Dw2Inval
-tr6, Test, 0, 6, Dw2Inval, Dw2Inval
-tr7, Test, 0, 7, Dw2Inval, Dw2Inval
+tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
+tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
+tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
+tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
+tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
+tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
+tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
+tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
// MMX and simd registers.
mm0, RegMMX, 0, 0, 29, 41
mm1, RegMMX, 0, 1, 30, 42