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Re: C.ADDI x0, 4: illegal instruction ?

On Wed, 26 Jun 2019 09:45:31 PDT (-0700), wrote:

    Hi all,

    I noticed binuntils 2.32 assembles the instruction c.addi x0, 4 without any error but from my understanding RISC-V spec defines that as an illegal instruction.

    Latest official user-level  spec version is 2.2, on page 82, C.ADDI instruction are not allowed to have rs1/rd equal to 0 if nzimm field different from 0. If both rd/rs1 and nzimm are 0, then instruction is actually C.NOP. So, "c.addi x0, 4" is an illegal instruction and assembler should give an error.

    Am I missing anything ?

The ISA manual says

   C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register
   rd then writes the result to rd. C.ADDI expands into addi rd, rd, nzimm[5:0].
   C.ADDI is only valid when rd = x0.  The code point with both rd=x0 and nzimm=0
   encodes the C.NOP instruction; the remaining code points with either rd=x0 or
   nzimm=0 encode HINTs.  C.ADDIW is an RV64C/RV128C-only instruction that
   performs the same computation but pro-

Right now in binutils we handle the HINT instruction by just allowing the
corresponding non-HINT instruction that would naturally encode as the same
bits.  This is a bit of a historical artifact: the ISA used to describe hints
as sub-types of other instructions, but now hints are described as explicit
HINT instruction with many different encoding formats.  This behavior is all
over the assembler, see the comments in opcodes/riscv-opc.c.

I don't think we can change the default behavior here, as that would be a
backwards-incompatible change.  I wouldn't be opposed to adding an explicit
HINT pneumonic that could encode all forms of hints and then something like
"-mexplicit-hints", just like we have "-mno-aliases", but I don't think that's
going to be high on anyone's priority list.

That said, if you (or someone else) wanted to start hacking on the RISC-V
binutils port this could be a good project.

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