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[PATCH] RISC-V: Make objdump disassembly work right for binary files.

Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN
which gets printed as big-endian.  But RISC-V instructions are always little
endian, so we can set endian_code correctly, and then set display_endian from
that.  This is similar to how the aarch64 support works, but without the
support for constant pools, as we don't have that on RISC-V.

Tested by hand on a binary file to verify I get the right result.  Also
tested with riscv{32,64}-{elf,linux} cross builds and check, with no



	PR binutils/24739
	* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
	Set info->display_endian to info->endian_code.
 opcodes/riscv-dis.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 764c4d4d25..40893c3dcb 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -395,9 +395,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
   insnlen = riscv_insn_length (word);
+  /* RISC-V instructions are always little-endian.  */
+  info->endian_code = BFD_ENDIAN_LITTLE;
   info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
   info->bytes_per_line = 8;
-  info->display_endian = info->endian;
+  /* We don't support constant pools, so this must be code.  */
+  info->display_endian = info->endian_code;
   info->insn_info_valid = 1;
   info->branch_delay_insns = 0;
   info->data_size = 0;

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