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Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
- From: Nick Clifton <nickc at redhat dot com>
- To: Peng Fan <peng dot fan at nxp dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Jan Kiszka <jan dot kiszka at siemens dot com>
- Date: Tue, 19 Feb 2019 15:41:13 +0000
- Subject: Re: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
- References: <DB7PR04MB4490DCC3F3454AB084EA1DC088660@DB7PR04MB4490.eurprd04.prod.outlook.com>
Hi Peng,
> Not sure this is bug or not, is my patch the correct fix?
> please help.
I think that you have reported this problem to the wrong mailing list...
> I did a fix to the code as below:
> --- a/hypervisor/arch/arm64/include/asm/bitops.h
> +++ b/hypervisor/arch/arm64/include/asm/bitops.h
This is not part of the binutils sources. :-)
For what it is worth, I think that your analysis is correct,
and that the warning message from the assembler is valid. So
patching the hypervisor code would be in order. I cannot say
whether the patch itself is correct however.
Cheers
Nick