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[PATCH] S12Z: Fix disassembly of indexed OPR operands with zero index.
- From: John Darrington <john at darrington dot wattle dot id dot au>
- To: binutils at sourceware dot org
- Cc: John Darrington <john at darrington dot wattle dot id dot au>
- Date: Thu, 3 Jan 2019 19:03:30 +0100
- Subject: [PATCH] S12Z: Fix disassembly of indexed OPR operands with zero index.
gas/
* testsuite/gas/jsr.s: New case.
* testsuite/gas/jsr.d: New case.
opcodes/
* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
---
gas/testsuite/gas/s12z/jsr.d | 1 +
gas/testsuite/gas/s12z/jsr.s | 3 ++-
opcodes/s12z-dis.c | 57 +++++++++++++++++++++-----------------------
3 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/gas/testsuite/gas/s12z/jsr.d b/gas/testsuite/gas/s12z/jsr.d
index c23f684176..cf37e6ea13 100644
--- a/gas/testsuite/gas/s12z/jsr.d
+++ b/gas/testsuite/gas/s12z/jsr.d
@@ -31,3 +31,4 @@ Disassembly of section .text:
2a: ab f9 be 91 jsr 114321
2e: ab fe 07 82 jsr \[492134\]
32: 66
+ 33: ab 40 jsr \(0,x\)
diff --git a/gas/testsuite/gas/s12z/jsr.s b/gas/testsuite/gas/s12z/jsr.s
index 80f0ff1422..fa761d33f7 100644
--- a/gas/testsuite/gas/s12z/jsr.s
+++ b/gas/testsuite/gas/s12z/jsr.s
@@ -1,5 +1,5 @@
jsr d2
- jsr (2, y)
+ jsr (2,y)
jsr (+y)
jsr (-y)
jsr (y+)
@@ -18,3 +18,4 @@
jsr 4021
jsr 114321
jsr [492134]
+ jsr (0,x)
diff --git a/opcodes/s12z-dis.c b/opcodes/s12z-dis.c
index 14176fb6d9..5db0b43562 100644
--- a/opcodes/s12z-dis.c
+++ b/opcodes/s12z-dis.c
@@ -282,36 +282,33 @@ opr_emit_disassembly (const struct operand *opr,
struct memory_operand *mo = (struct memory_operand *) opr;
(*info->fprintf_func) (info->stream, "%c", mo->indirect ? '[' : '(');
- if (mo->base_offset != 0)
- {
- (*info->fprintf_func) (info->stream, "%d", mo->base_offset);
- }
- else if (mo->n_regs > 0)
- {
- const char *fmt;
- switch (mo->mutation)
- {
- case OPND_RM_PRE_DEC:
- fmt = "-%s";
- break;
- case OPND_RM_PRE_INC:
- fmt = "+%s";
- break;
- case OPND_RM_POST_DEC:
- fmt = "%s-";
- break;
- case OPND_RM_POST_INC:
- fmt = "%s+";
- break;
- case OPND_RM_NONE:
- default:
- fmt = "%s";
- break;
- }
- (*info->fprintf_func) (info->stream, fmt,
- registers[mo->regs[0]].name);
- used_reg = 1;
- }
+ const char *fmt;
+ assert (mo->mutation == OPND_RM_NONE || mo->n_regs == 1);
+ switch (mo->mutation)
+ {
+ case OPND_RM_PRE_DEC:
+ fmt = "-%s";
+ break;
+ case OPND_RM_PRE_INC:
+ fmt = "+%s";
+ break;
+ case OPND_RM_POST_DEC:
+ fmt = "%s-";
+ break;
+ case OPND_RM_POST_INC:
+ fmt = "%s+";
+ break;
+ case OPND_RM_NONE:
+ default:
+ if (mo->n_regs < 2)
+ (*info->fprintf_func) (info->stream, (mo->n_regs == 0) ? "%d" : "%d,", mo->base_offset);
+ fmt = "%s";
+ break;
+ }
+ if (mo->n_regs > 0)
+ (*info->fprintf_func) (info->stream, fmt,
+ registers[mo->regs[0]].name);
+ used_reg = 1;
if (mo->n_regs > used_reg)
{
--
2.11.0