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Re: [PATCH 02/12] x86: fold various AVX512VL templates into their AVX512F counterparts
On Wed, May 30, 2018 at 7:46 AM, Jan Beulich <JBeulich@suse.com> wrote:
> gas/
> 2018-05-30 Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (is_evex_encoding): Also check disp8memshift.
> (optimize_encoding): Also cover templates without cpuavx512vl
> allowing for zmmword and having a ymmword actual.
> (check_VecOperands): Handle DISP8_SHIFT_VL.
> * testsuite/gas/i386/noavx512-2.l: Adjust expectations.
>
> opcodes/
> 2018-05-30 Jan Beulich <jbeulich@suse.com>
>
> * i386-gen.c (stringify, _stringify, opcode_modifier_shorthands):
> New.
> (set_bitfield_from_shorthand): Handle opcode_modifier_shorthands.
> * i386-opc.h (DISP8_SHIFT_VL): New.
> * i386-opc.tbl: Fold AVX512VL templates into their respective
> AVX512F where possible.
> * i386-tbl.h: Re-generate.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -3466,7 +3466,7 @@ build_vex_prefix (const insn_template *t
> static INLINE bfd_boolean
> is_evex_encoding (const insn_template *t)
> {
> - return t->opcode_modifier.evex
> + return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
> || t->opcode_modifier.broadcast || t->opcode_modifier.masking
> || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
> }
> @@ -3889,6 +3889,8 @@ optimize_encoding (void)
> && is_evex_encoding (&i.tm)
> && (i.vec_encoding != vex_encoding_evex
> || i.tm.cpu_flags.bitfield.cpuavx512vl
> + || (i.tm.operand_types[2].bitfield.zmmword
> + && i.types[2].bitfield.ymmword)
> || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
> && ((i.tm.base_opcode == 0x55
> || i.tm.base_opcode == 0x6655
> @@ -5207,8 +5209,47 @@ check_VecOperands (const insn_template *
> {
> if (i.broadcast)
> i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
> - else
> + else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
> i.memshift = t->opcode_modifier.disp8memshift;
> + else
> + {
> + const i386_operand_type *type = NULL;
> +
> + i.memshift = 0;
> + for (op = 0; op < i.operands; op++)
> + if (operand_type_check (i.types[op], anymem))
> + {
> + if (t->operand_types[op].bitfield.xmmword
> + + t->operand_types[op].bitfield.ymmword
> + + t->operand_types[op].bitfield.zmmword <= 1)
> + type = &t->operand_types[op];
> + else if (!i.types[op].bitfield.unspecified)
> + type = &i.types[op];
> + }
> + else if (i.types[op].bitfield.regsimd)
> + {
> + if (i.types[op].bitfield.zmmword)
> + i.memshift = 6;
> + else if (i.types[op].bitfield.ymmword && i.memshift < 5)
> + i.memshift = 5;
> + else if (i.types[op].bitfield.xmmword && i.memshift < 4)
> + i.memshift = 4;
> + }
> +
> + if (type)
> + {
> + if (type->bitfield.zmmword)
> + i.memshift = 6;
> + else if (type->bitfield.ymmword)
> + i.memshift = 5;
> + else if (type->bitfield.xmmword)
> + i.memshift = 4;
> + }
> +
> + /* For the check in fits_in_disp8(). */
> + if (i.memshift == 0)
> + i.memshift = -1;
> + }
>
> for (op = 0; op < i.operands; op++)
> if (operand_type_check (i.types[op], disp)
> --- a/gas/testsuite/gas/i386/noavx512-2.l
> +++ b/gas/testsuite/gas/i386/noavx512-2.l
> @@ -5,8 +5,8 @@
> .*:30: Error: .*unsupported instruction.*
> .*:32: Error: .*unsupported instruction.*
> .*:33: Error: .*unsupported instruction.*
> -.*:36: Error: .*unsupported masking.*
> -.*:37: Error: .*unsupported masking.*
> +.*:36: Error: .*unsupported instruction.*
> +.*:37: Error: .*unsupported instruction.*
> .*:39: Error: .*unsupported instruction.*
> .*:40: Error: .*unsupported instruction.*
> .*:43: Error: .*unsupported instruction.*
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -30,6 +30,9 @@
> #include <libintl.h>
> #define _(String) gettext (String)
>
> +#define _stringify(x) #x
> +#define stringify(x) _stringify(x)
> +
> static const char *program_name = NULL;
> static int debug = 0;
>
> @@ -366,6 +369,11 @@ static const initializer operand_type_sh
> { "RegZMM", "RegSIMD|Zmmword" },
> };
>
> +static const initializer opcode_modifier_shorthands[] =
> +{
> + { "Disp8ShiftVL", "Disp8MemShift=" stringify(DISP8_SHIFT_VL) },
> +};
> +
> static initializer operand_type_init[] =
> {
> { "OPERAND_TYPE_NONE",
> @@ -841,6 +849,22 @@ set_bitfield_from_shorthand (char *f, bi
> last = init + strlen (init);
> for (next = init; next && next < last; )
> {
> + str = next_field (next, '|', &next, last);
> + if (str)
> + set_bitfield (str, array, 1, size, lineno);
> + }
> + free (init);
> + return 0;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE (opcode_modifier_shorthands); i++)
> + if (strcmp (opcode_modifier_shorthands[i].name, f) == 0)
> + {
> + /* Turn on selective bits. */
> + char *init = xstrdup (opcode_modifier_shorthands[i].init);
> + last = init + strlen (init);
> + for (next = init; next && next < last; )
> + {
> str = next_field (next, '|', &next, last);
> if (str)
> set_bitfield (str, array, 1, size, lineno);
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -569,7 +569,8 @@ enum
> /* Supress All Exceptions is supported. */
> SAE,
>
> - /* Copressed Disp8*N attribute. */
> + /* Compressed Disp8*N attribute. */
> +#define DISP8_SHIFT_VL 7
> Disp8MemShift,
>
> /* Default mask isn't allowed. */
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -2914,22 +2914,22 @@ kshiftrw, 3, 0x6630, None, 1, CpuAVX512F
>
> kunpckbw, 3, 0x664B, None, 1, CpuAVX512F, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
>
> -vaddpd, 3, 0x6658, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
EVex=1 is removed. But it isn't mentioned.
> +vaddpd, 3, 0x6658, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
>
Where is Disp8ShiftVL defined?
--
H.J.