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Re: [PATCH 3/3] Enable Intel MOVDIRI, MOVDIR64B instructions.
On Tue, May 8, 2018 at 11:41 PM, Jan Beulich <jbeulich@suse.com> wrote:
>>>> "H.J. Lu" <hjl.tools@gmail.com> 05/07/18 7:55 PM >>>
>>On Thu, Apr 26, 2018 at 11:40 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 26.04.18 at 21:49, <igor.v.tsimbalist@intel.com> wrote:
>>>>+movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|ZMMword|BaseIndex|Disp8|Disp32|Disp32S, Reg16|Reg32 }
>>>>+movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|ZMMword|BaseIndex|Disp8|Disp32|Disp32S, Reg32|Reg64 }
>>>
>>> Almost all the same here. Additionally, while I can see that ZMMword fits
>>> the 64-byte operand size, I really think it would look rather odd to have
>>> "zmmword ptr" used on an operand here. Simply require no operand size
>>> prefix (in Intel syntax mode), just like you make the disassembler not
>>> produce any?
>>
>>Fixed. We need 2 templates since Reg16 isn't supported in 64-bit mode.
>
> Well, yes, with the current code in tc-i386.c this is unavoidable. I have a
> respective item on my todo list already, since it would also help SVM insns
> (which currently wrongly disallow Reg16) without having to duplicate their
> templates.
>
> In any event - please drop the now redundant Disp<N> from all three templates.
>
This is what I checked in.
Thanks.
--
H.J.
From 06cfb1c89510d08217da8b3ccea05ecd4cdb5bc6 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 9 May 2018 11:17:26 -0700
Subject: [PATCH] x86: Remove Disp<N> from movidir{i,64b}
* i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
---
opcodes/ChangeLog | 4 ++++
opcodes/i386-opc.tbl | 6 +++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4dfd5011a9..0586af694c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
+
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* cr16-opc.c (cr16_instruction): Comment typo fix.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b3ccaa4f8c..201586cbcc 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5832,9 +5832,9 @@ cldemote, 1, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lS
// MOVDIR[I,64B] instructions.
-movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
-movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|BaseIndex|Disp8|Disp16|Disp32, Reg16|Reg32 }
-movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg32|Reg64 }
+movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32 }
+movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg32|Reg64 }
// MOVEDIR instructions end.
--
2.17.0