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Re: [PATCH][AARCH64] Allow the TLS GD sequence to be split

On Thu, Feb 21, 2013 at 12:47:39PM -0000, Sofiane Naci wrote:
> Hi,
> The AArch64 BFD linker currently expects that the TLS GD instructions are
> sequential:
>    add     x0, x0, #0x0     R_AARCH64_TLSGD_ADD_LO12_NC
>    bl      __tls_get_addr   R_AARCH64_CALL26
>    nop
> Given that we have different relocs on the ADD and the BL, we can improve
> relaxation to work on the two instructions even when they are not
> sequential. This will allow the compiler to break the sequence above if
> better scheduling can be achieved.

PowerPC went the same route.  We initially constrained the insn
setting up the __tls_get_addr argument to be adjacent to the call,
then tried the same idea you're using here.  It doesn't work in all
situations.  For example, gcc can schedule other insns requiring
relocations between the two of interest here.  Loop optimization can
reorder insns, so the call appears at a lower address than the arg
setup.  Worse, hot/cold partitioning can move the call to a different
section entirely from the arg setup insn.  The solution is to mark the
call with a second reloc that specifies the same symbol/addend as that
on the arg setup insn, and also says whether the call is for a GD or
LD sequence.  eg. a powerpc64 global dynamic call looks like:

Code sequence		Reloc			Sym
 addi 3,2,x@got@tlsgd	R_PPC64_GOT_TLSGD16	x
 bl __tls_get_addr	R_PPC64_TLSGD		x
			R_PPC64_REL24		__tls_get_addr

The R_PPC64_GOT_TLSGD16 tells the linker that the insn at that
location is the arg setup insn of a GD tls sequence.  The
R_PPC64_TLSGD marker that it is the call for a GD tls sequence.  If
such a sequence for "x" can be optimized, the linker can safely do so
for each insn independently.

Alan Modra
Australia Development Lab, IBM

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