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RE: [toolchain-devel] [Patch] set unused SRCx fields to all 1s for dspalu32 instrs

Thanks Jie.

Take two.

Stu

Stuart Henderson  <shenders@gcc.gnu.org>
gas:
   * config/bfin-parse.y (asm_1): Set SRCx fields to all 1s for dspalu32 instrs
   that don't use them.

gas/testsuite:
   * gas/bfin/move.d: Update SRCx field expectations.
   * gas/bfin/move2.d: Likewise.
   * gas/bfin/parallel.d: Likewise.
   * gas/bfin/parallel2.d: Likewise.
   * gas/bfin/parallel3.d: Likewise.
   * gas/bfin/parallel4.d: Likewise.
   * gas/bfin/video.d: Likewise.
   * gas/bfin/video2.d: Likewise.


diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 797664a..dfa1079 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -166,6 +166,9 @@ char *current_inputline;
 extern char *yytext;
 int yyerror (char *);

+/* Used to set SRCx fields to all 1s as described in the PRM.  */
+Register reg7 = {REG_R7, 0};
+
 void error (char *format, ...)
 {
     va_list ap;
@@ -801,7 +804,7 @@ asm_1:
          if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
            {
              notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
-             $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
+             $$ = DSP32ALU (11, 0, 0, &$1, &reg7, &reg7, 0, 0, 0);
            }
          else
            return yyerror ("Register mismatch");
@@ -811,7 +814,7 @@ asm_1:
          if (!IS_A1 ($4) && IS_A1 ($5))
            {
              notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
-             $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
+             $$ = DSP32ALU (11, IS_H ($1), 0, &$1, &reg7, &reg7, 0, 0, 1);
            }
          else
            return yyerror ("Register mismatch");
@@ -898,7 +901,7 @@ asm_1:
          if (IS_DREG ($1) && IS_DREG ($7))
            {
              notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
-             $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
+             $$ = DSP32ALU (12, 0, &$1, &$7, &reg7, &reg7, 0, 0, 1);
            }
          else
            return yyerror ("Register mismatch");
@@ -914,14 +917,14 @@ asm_1:
              && IS_A1 ($9) && !IS_A1 ($11))
            {
              notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
-             $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
+             $$ = DSP32ALU (17, 0, &$1, &$7, &reg7, &reg7, $12.s0, $12.x0, 0);

            }
          else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
                   && !IS_A1 ($9) && IS_A1 ($11))
            {
              notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
-             $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
+             $$ = DSP32ALU (17, 0, &$1, &$7, &reg7, &reg7, $12.s0, $12.x0, 1);
            }
          else
            return yyerror ("Register mismatch");
@@ -995,7 +998,7 @@ asm_1:
        | a_assign ABS REG_A
        {
          notethat ("dsp32alu: Ax = ABS Ax\n");
-         $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
+         $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, &reg7, &reg7, 0, 0, IS_A1 ($3));
        }
        | A_ZERO_DOT_L ASSIGN HALF_REG
        {
@@ -1162,7 +1165,7 @@ asm_1:
        | a_assign MINUS REG_A
        {
          notethat ("dsp32alu: Ax = - Ax\n");
-         $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
+         $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, &reg7, &reg7, 0, 0, IS_A1 ($3));
        }
        | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
        {
@@ -1175,7 +1178,7 @@ asm_1:
          if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
            {
              notethat ("dsp32alu: A1 = A0 = 0\n");
-             $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
+             $$ = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, 0, 0, 2);
            }
          else
            return yyerror ("Bad value, 0 expected");
@@ -1187,7 +1190,7 @@ asm_1:
          if (REG_SAME ($1, $2))
            {
              notethat ("dsp32alu: Ax = Ax (S)\n");
-             $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
+             $$ = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, 1, 0, IS_A1 ($1));
            }
          else
            return yyerror ("Registers must be equal");
@@ -1231,7 +1234,7 @@ asm_1:
          if (!REG_SAME ($1, $2))
            {
              notethat ("dsp32alu: An = Am\n");
-             $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
+             $$ = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, IS_A1 ($1), 0, 3);
            }
          else
            return yyerror ("Accu reg arguments must differ");
@@ -1351,12 +1354,12 @@ asm_1:
          if (IS_DREG ($1) && $3.regno == REG_A0x)
            {
              notethat ("dsp32alu: dregs_lo = A0.x\n");
-             $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
+             $$ = DSP32ALU (10, 0, 0, &$1, &reg7, &reg7, 0, 0, 0);
            }
          else if (IS_DREG ($1) && $3.regno == REG_A1x)
            {
              notethat ("dsp32alu: dregs_lo = A1.x\n");
-             $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
+             $$ = DSP32ALU (10, 0, 0, &$1, &reg7, &reg7, 0, 0, 1);
            }
          else
            return yyerror ("Register mismatch");
@@ -1389,7 +1392,7 @@ asm_1:
          if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
            {
              notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
-             $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
+             $$ = DSP32ALU (16, 0, 0, 0, &reg7, &reg7, 0, 0, 3);
            }
          else
            return yyerror ("Register mismatch");
@@ -1400,7 +1403,7 @@ asm_1:
          if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
            {
              notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
-             $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
+             $$ = DSP32ALU (14, 0, 0, 0, &reg7, &reg7, 0, 0, 3);
            }
          else
            return yyerror ("Register mismatch");
@@ -1411,7 +1414,7 @@ asm_1:
          if (!IS_A1 ($1) && IS_A1 ($2))
            {
              notethat ("dsp32alu: A0 -= A1\n");
-             $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
+             $$ = DSP32ALU (11, 0, 0, 0, &reg7, &reg7, $3.r0, 0, 3);
            }
          else
            return yyerror ("Register mismatch");
@@ -1471,7 +1474,7 @@ asm_1:
          if (!IS_A1 ($1) && IS_A1 ($3))
            {
              notethat ("dsp32alu: A0 += A1 (W32)\n");
-             $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
+             $$ = DSP32ALU (11, 0, 0, 0, &reg7, &reg7, $4.r0, 0, 2);
            }
          else
            return yyerror ("Register mismatch");
@@ -1550,7 +1553,7 @@ asm_1:
          if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
            {
              notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
-             $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
+             $$ = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, 1, 0, 2);
            }
          else
            return yyerror ("Register mismatch");
diff --git a/gas/testsuite/gas/bfin/move.d b/gas/testsuite/gas/bfin/move.d
index d81f81f..7dc8dbb 100644
--- a/gas/testsuite/gas/bfin/move.d
+++ b/gas/testsuite/gas/bfin/move.d
@@ -56,8 +56,8 @@ Disassembly of section .text:
 00000066 <move_register_half>:
   66:  09 c4 28 40     A0.X = R5.L;
   6a:  09 c4 10 c0     A1.X = R2.L;
-  6e:  0a c4 [0|3][0|6] 00     R0.L = A0.X;
-  72:  0a c4 [0|3][0|6] 4e     R7.L = A1.X;
+  6e:  0a c4 3f 00     R0.L = A0.X;
+  72:  0a c4 3f 4e     R7.L = A1.X;
   76:  09 c4 18 00     A0.L = R3.L;
   7a:  09 c4 20 80     A1.L = R4.L;
   7e:  29 c4 30 00     A0.H = R6.H;
diff --git a/gas/testsuite/gas/bfin/move2.d b/gas/testsuite/gas/bfin/move2.d
index 5c64252..1e82179 100644
--- a/gas/testsuite/gas/bfin/move2.d
+++ b/gas/testsuite/gas/bfin/move2.d
@@ -279,12 +279,12 @@ Disassembly of section .text:
  248:  09 c4 08 40     A0.X = R1.L;
  24c:  09 c4 00 c0     A1.X = R0.L;
  250:  09 c4 08 c0     A1.X = R1.L;
- 254:  0a c4 [0|3][0|6] 00     R0.L = A0.X;
- 258:  0a c4 [0|3][0|6] 02     R1.L = A0.X;
- 25c:  0a c4 [0|3][0|6] 0e     R7.L = A0.X;
- 260:  0a c4 [0|3][0|6] 40     R0.L = A1.X;
- 264:  0a c4 [0|3][0|6] 42     R1.L = A1.X;
- 268:  0a c4 [0|3][0|6] 4e     R7.L = A1.X;
+ 254:  0a c4 3f 00     R0.L = A0.X;
+ 258:  0a c4 3f 02     R1.L = A0.X;
+ 25c:  0a c4 3f 0e     R7.L = A0.X;
+ 260:  0a c4 3f 40     R0.L = A1.X;
+ 264:  0a c4 3f 42     R1.L = A1.X;
+ 268:  0a c4 3f 4e     R7.L = A1.X;
  26c:  09 c4 00 00     A0.L = R0.L;
  270:  09 c4 08 00     A0.L = R1.L;
  274:  09 c4 30 00     A0.L = R6.L;
diff --git a/gas/testsuite/gas/bfin/parallel.d b/gas/testsuite/gas/bfin/parallel.d
index bd4269c..6445bd3 100644
--- a/gas/testsuite/gas/bfin/parallel.d
+++ b/gas/testsuite/gas/bfin/parallel.d
@@ -29,15 +29,15 @@ Disassembly of section .text:
   54:  f8 90 00 00
   58:  06 ce 02 ce     R7.L = ONES R2 \|\| P1 = \[P5 \+ 0x18\] \|\| NOP;
   5c:  a9 ad 00 00
-  60:  10 cc 00 00     A0 = ABS A0 \|\| P2 = \[SP \+ 0x3c\] \|\| R0 = \[I0\];
+  60:  10 cc 3f 00     A0 = ABS A0 \|\| P2 = \[SP \+ 0x3c\] \|\| R0 = \[I0\];
   64:  f2 af 00 9d
-  68:  10 cc 00 40     A0 = ABS A1 \|\| P3 = \[FP -0x3c\] \|\| R1 = \[I1 \+\+ M0\];
+  68:  10 cc 3f 40     A0 = ABS A1 \|\| P3 = \[FP -0x3c\] \|\| R1 = \[I1 \+\+ M0\];
   6c:  1b b9 89 9d
-  70:  30 cc 00 00     A1 = ABS A0 \|\| P4 = \[FP -0x4\] \|\| R2 = \[I1\+\+\];
+  70:  30 cc 3f 00     A1 = ABS A0 \|\| P4 = \[FP -0x4\] \|\| R2 = \[I1\+\+\];
   74:  fc b9 0a 9c
-  78:  30 cc 00 40     A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\];
+  78:  30 cc 3f 40     A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\];
   7c:  77 91 93 9c
-  80:  10 cc 00 c0     A1 = ABS A1, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\];
+  80:  10 cc 3f c0     A1 = ABS A1, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\];
   84:  ac a3 40 9d
   88:  07 cc 10 80     R0 = ABS R2 \|\| B\[SP\] = R0 \|\| R1.H = W\[I1\+\+\];
   8c:  30 9b 49 9c
@@ -75,19 +75,19 @@ Disassembly of section .text:
  10c:  12 9b 08 9c
  110:  07 cc 38 48     R4 = MIN \(R7, R0\) \|\| B\[P3\] = R2 \|\| R1 = \[I1\+\+\];
  114:  1a 9b 09 9c
- 118:  0b cc 00 c0     A0 -= A1 \|\| B\[P4\] = R2 \|\| R2 = \[I1\+\+\];
+ 118:  0b cc 3f c0     A0 -= A1 \|\| B\[P4\] = R2 \|\| R2 = \[I1\+\+\];
  11c:  22 9b 0a 9c
- 120:  0b cc 00 e0     A0 -= A1 \(W32\) \|\| B\[P5\] = R2 \|\| R3 = \[I1\+\+\];
+ 120:  0b cc 3f e0     A0 -= A1 \(W32\) \|\| B\[P5\] = R2 \|\| R3 = \[I1\+\+\];
  124:  2a 9b 0b 9c
- 128:  0b cc 00 80     A0 \+= A1 \|\| B\[SP\] = R2 \|\| R4 = \[I1\+\+\];
+ 128:  0b cc 3f 80     A0 \+= A1 \|\| B\[SP\] = R2 \|\| R4 = \[I1\+\+\];
  12c:  32 9b 0c 9c
- 130:  0b cc 00 a0     A0 \+= A1 \(W32\) \|\| B\[FP\] = R2 \|\| R5 = \[I1\+\+\];
+ 130:  0b cc 3f a0     A0 \+= A1 \(W32\) \|\| B\[FP\] = R2 \|\| R5 = \[I1\+\+\];
  134:  3a 9b 0d 9c
- 138:  0b cc 00 0e     R7 = \(A0 \+= A1\) \|\| B\[SP\] = R3 \|\| R6 = \[I1\+\+\];
+ 138:  0b cc 3f 0e     R7 = \(A0 \+= A1\) \|\| B\[SP\] = R3 \|\| R6 = \[I1\+\+\];
  13c:  33 9b 0e 9c
- 140:  0b cc 00 4c     R6.L = \(A0 \+= A1\) \|\| B\[FP\] = R3 \|\| R7 = \[I1\+\+\];
+ 140:  0b cc 3f 4c     R6.L = \(A0 \+= A1\) \|\| B\[FP\] = R3 \|\| R7 = \[I1\+\+\];
  144:  3b 9b 0f 9c
- 148:  2b cc 00 40     R0.H = \(A0 \+= A1\) \|\| B\[P0\] = R3 \|\| R7 = \[I0\+\+\];
+ 148:  2b cc 3f 40     R0.H = \(A0 \+= A1\) \|\| B\[P0\] = R3 \|\| R7 = \[I0\+\+\];
  14c:  03 9b 07 9c
  150:  00 ca 0a 24     R0.L = R1.H \* R2.L \|\| B\[P1\] = R3 \|\| R1 = \[I0\+\+\];
  154:  0b 9b 01 9c
@@ -189,25 +189,25 @@ Disassembly of section .text:
  2d4:  c0 8a 2e 9c
  2d8:  07 cc 10 ee     R7 = -R2 \(S\) \|\| W\[P0\] = R4.L \|\| R5.L = W\[I2\+\+\];
  2dc:  00 8b 35 9c
- 2e0:  0e cc 00 00     A0 = -A0 \|\| W\[P0\] = R5.L \|\| R4.L = W\[I3\+\+\];
+ 2e0:  0e cc 3f 00     A0 = -A0 \|\| W\[P0\] = R5.L \|\| R4.L = W\[I3\+\+\];
  2e4:  40 8b 3c 9c
- 2e8:  0e cc 00 40     A0 = -A1 \|\| W\[P0\] = R6.L \|\| R3.L = W\[I3--\];
+ 2e8:  0e cc 3f 40     A0 = -A1 \|\| W\[P0\] = R6.L \|\| R3.L = W\[I3--\];
  2ec:  80 8b bb 9c
- 2f0:  2e cc 00 00     A1 = -A0 \|\| W\[P0\] = R7.L \|\| R2.L = W\[I1\+\+\];
+ 2f0:  2e cc 3f 00     A1 = -A0 \|\| W\[P0\] = R7.L \|\| R2.L = W\[I1\+\+\];
  2f4:  c0 8b 2a 9c
- 2f8:  2e cc 00 40     A1 = -A1 \|\| W\[P1\] = R0 \|\| R1.L = W\[I2--\];
+ 2f8:  2e cc 3f 40     A1 = -A1 \|\| W\[P1\] = R0 \|\| R1.L = W\[I2--\];
  2fc:  08 97 b1 9c
- 300:  0e cc 00 c0     A1 = -A1, A0 = -A0 \|\| W\[P1\] = R1 \|\| R0.L = W\[I1--\];
+ 300:  0e cc 3f c0     A1 = -A1, A0 = -A0 \|\| W\[P1\] = R1 \|\| R0.L = W\[I1--\];
  304:  09 97 a8 9c
  308:  0c cc 18 ca     R5.L = R3 \(RND\) \|\| W\[P1\] = R2 \|\| R0 = \[I0 \+\+ M3\];
  30c:  0a 97 e0 9d
  310:  2c cc 00 cc     R6.H = R0 \(RND\) \|\| W\[P1\] = R3 \|\| R1 = \[I1 \+\+ M2\];
  314:  0b 97 c9 9d
- 318:  08 cc 00 20     A0 = A0 \(S\) \|\| W\[P1\] = R4 \|\| R2 = \[I2 \+\+ M1\];
+ 318:  08 cc 3f 20     A0 = A0 \(S\) \|\| W\[P1\] = R4 \|\| R2 = \[I2 \+\+ M1\];
  31c:  0c 97 b2 9d
- 320:  08 cc 00 60     A1 = A1 \(S\) \|\| W\[P1\] = R5 \|\| R3 = \[I3 \+\+ M0\];
+ 320:  08 cc 3f 60     A1 = A1 \(S\) \|\| W\[P1\] = R5 \|\| R3 = \[I3 \+\+ M0\];
  324:  0d 97 9b 9d
- 328:  08 cc 00 a0     A1 = A1 \(S\), A0 = A0 \(S\) \|\| R6 = W\[P1\] \(Z\) \|\| \[I0\] = R0;
+ 328:  08 cc 3f a0     A1 = A1 \(S\), A0 = A0 \(S\) \|\| R6 = W\[P1\] \(Z\) \|\| \[I0\] = R0;
  32c:  0e 95 00 9f
  330:  05 ce 00 0a     R5.L = SIGNBITS R0 \|\| R7 = W\[P1\] \(Z\) \|\| \[I1\] = R0;
  334:  0f 95 08 9f
@@ -225,15 +225,15 @@ Disassembly of section .text:
  364:  01 9c 00 00
  368:  03 c8 00 18     MNOP \|\| P0 = \[FP \+ 0x14\] \|\| R0 = \[I2\+\+\];
  36c:  78 ad 10 9c
- 370:  0a cc 00 08     R4.L = A0.X \|\| R6 = \[FP \+ 0x3c\] \|\| R4.H = W\[I1\+\+\];
+ 370:  0a cc 3f 08     R4.L = A0.X \|\| R6 = \[FP \+ 0x3c\] \|\| R4.H = W\[I1\+\+\];
  374:  fe a3 4c 9c
- 378:  0a cc 00 08     R4.L = A0.X \|\| R4.H = W\[I1\+\+\] \|\| W\[I0\] = R4.H;
+ 378:  0a cc 3f 08     R4.L = A0.X \|\| R4.H = W\[I1\+\+\] \|\| W\[I0\] = R4.H;
  37c:  4c 9c 44 9f
- 380:  0a cc 00 08     R4.L = A0.X \|\| W\[I1\+\+\] = R4.L \|\| R4.H = W\[I0--\];
+ 380:  0a cc 3f 08     R4.L = A0.X \|\| W\[I1\+\+\] = R4.L \|\| R4.H = W\[I0--\];
  384:  2c 9e c4 9c
- 388:  0a cc 00 48     R4.L = A1.X \|\| R6 = B\[SP--\] \(Z\) \|\| R4.H = W\[I1\+\+\];
+ 388:  0a cc 3f 48     R4.L = A1.X \|\| R6 = B\[SP--\] \(Z\) \|\| R4.H = W\[I1\+\+\];
  38c:  b6 98 4c 9c
- 390:  0b cc 00 a0     A0 \+= A1 \(W32\) \|\| R3.L = W\[I0\] \|\| R0 = \[I0 \+\+ M3\];
+ 390:  0b cc 3f a0     A0 \+= A1 \(W32\) \|\| R3.L = W\[I0\] \|\| R0 = \[I0 \+\+ M3\];
  394:  23 9d e0 9d
- 398:  0b cc 00 c0     A0 -= A1 \|\| R0 = W\[P0\+\+\] \(X\) \|\| W\[I0\+\+\] = R3.L;
+ 398:  0b cc 3f c0     A0 -= A1 \|\| R0 = W\[P0\+\+\] \(X\) \|\| W\[I0\+\+\] = R3.L;
  39c:  40 94 23 9e
diff --git a/gas/testsuite/gas/bfin/parallel2.d b/gas/testsuite/gas/bfin/parallel2.d
index 3a07b86..3ec0dca 100644
--- a/gas/testsuite/gas/bfin/parallel2.d
+++ b/gas/testsuite/gas/bfin/parallel2.d
@@ -5,9 +5,9 @@
 Disassembly of section .text:

 00000000 <.text>:
-   0:  08 cc 00 c0     A0 = A1 \|\| P0 = \[SP \+ 0x14\] \|\| NOP;
+   0:  08 cc 3f c0     A0 = A1 \|\| P0 = \[SP \+ 0x14\] \|\| NOP;
    4:  70 ad 00 00
-   8:  08 cc 00 e0     A1 = A0 \|\| P0 = \[P5 \+ 0x18\] \|\| NOP;
+   8:  08 cc 3f e0     A1 = A0 \|\| P0 = \[P5 \+ 0x18\] \|\| NOP;
    c:  a8 ad 00 00
   10:  09 cc 00 20     A0 = R0 \|\| P0 = \[P4 \+ 0x1c\] \|\| NOP;
   14:  e0 ad 00 00
@@ -29,9 +29,9 @@ Disassembly of section .text:
   54:  e0 af 00 00
   58:  09 cc 10 c0     A1.X = R2.L \|\| R0 = \[I0 \+\+ M0\] \|\| NOP;
   5c:  80 9d 00 00
-  60:  0a cc 00 00     R0.L = A0.X \|\| R1 = \[I0 \+\+ M1\] \|\| NOP;
+  60:  0a cc 3f 00     R0.L = A0.X \|\| R1 = \[I0 \+\+ M1\] \|\| NOP;
   64:  a1 9d 00 00
-  68:  0a cc 00 4e     R7.L = A1.X \|\| R0 = \[I0 \+\+ M2\] \|\| NOP;
+  68:  0a cc 3f 4e     R7.L = A1.X \|\| R0 = \[I0 \+\+ M2\] \|\| NOP;
   6c:  c0 9d 00 00
   70:  09 cc 18 00     A0.L = R3.L \|\| R0 = \[I0 \+\+ M3\] \|\| NOP;
   74:  e0 9d 00 00
diff --git a/gas/testsuite/gas/bfin/parallel3.d b/gas/testsuite/gas/bfin/parallel3.d
index 9f23c59..aa3669c 100644
--- a/gas/testsuite/gas/bfin/parallel3.d
+++ b/gas/testsuite/gas/bfin/parallel3.d
@@ -47,9 +47,9 @@ Disassembly of section .text:
   9c:  58 93 00 00
   a0:  04 cc 39 a6     R0 = R7 \+ R1, R3 = R7 - R1 \(S\) \|\| \[P3\+\+\] = P0 \|\| NOP;
   a4:  58 92 00 00
-  a8:  11 cc c0 0b     R7 = A1 \+ A0, R5 = A1 - A0 \(NS\) \|\| \[P3--\] = P0 \|\| NOP;
+  a8:  11 cc ff 0b     R7 = A1 \+ A0, R5 = A1 - A0 \(NS\) \|\| \[P3--\] = P0 \|\| NOP;
   ac:  d8 92 00 00
-  b0:  11 cc c0 6c     R3 = A0 \+ A1, R6 = A0 - A1 \(S\) \|\| \[P3 \+ 0x1c\] = P0 \|\| NOP;
+  b0:  11 cc ff 6c     R3 = A0 \+ A1, R6 = A0 - A1 \(S\) \|\| \[P3 \+ 0x1c\] = P0 \|\| NOP;
   b4:  d8 bd 00 00
   b8:  81 ce 8b 03     R1 = R3 >>> 0xf \(V\) \|\| \[P3 \+ 0x18\] = P0 \|\| NOP;
   bc:  98 bd 00 00
diff --git a/gas/testsuite/gas/bfin/parallel4.d b/gas/testsuite/gas/bfin/parallel4.d
index 02863f9..0e1c37c 100644
--- a/gas/testsuite/gas/bfin/parallel4.d
+++ b/gas/testsuite/gas/bfin/parallel4.d
@@ -21,7 +21,7 @@ Disassembly of section .text:
   34:  10 9f 00 00
   38:  37 cc 02 24     R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\) \|\| \[I2\+\+\] = R0 \|\| NOP;
   3c:  10 9e 00 00
-  40:  0c cc 40 45     R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H \|\| \[I2--\] = R0 \|\| NOP;
+  40:  0c cc 7f 45     R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H \|\| \[I2--\] = R0 \|\| NOP;
   44:  90 9e 00 00
   48:  15 cc 82 06     \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\) \|\| \[I3\] = R0 \|\| NOP;
   4c:  18 9f 00 00
diff --git a/gas/testsuite/gas/bfin/video.d b/gas/testsuite/gas/bfin/video.d
index 0fafc06..4c16866 100644
--- a/gas/testsuite/gas/bfin/video.d
+++ b/gas/testsuite/gas/bfin/video.d
@@ -18,7 +18,7 @@ Disassembly of section .text:
 [ 0-9a-f]+:    37 c4 02 24     R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\);

 [0-9a-f]+ <dual16>:
-[ 0-9a-f]+:    0c c4 40 45     R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H;
+[ 0-9a-f]+:    0c c4 7f 45     R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H;

 [0-9a-f]+ <byteop16p>:
 [ 0-9a-f]+:    15 c4 82 06     \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\);
diff --git a/gas/testsuite/gas/bfin/video2.d b/gas/testsuite/gas/bfin/video2.d
index 98f2239..eba54fe 100644
--- a/gas/testsuite/gas/bfin/video2.d
+++ b/gas/testsuite/gas/bfin/video2.d
@@ -50,10 +50,10 @@ Disassembly of section .text:
 [ 0-9a-f]+:    37 c4 10 0a     R5 = BYTEOP3P \(R3:2, R1:0\) \(HI\);
 [ 0-9a-f]+:    17 c4 10 2c     R6 = BYTEOP3P \(R3:2, R1:0\) \(LO, R\);
 [ 0-9a-f]+:    37 c4 10 2e     R7 = BYTEOP3P \(R3:2, R1:0\) \(HI, R\);
-[ 0-9a-f]+:    0c c4 00 42     R0 = A1.L \+ A1.H, R1 = A0.L \+ A0.H;
-[ 0-9a-f]+:    0c c4 80 46     R2 = A1.L \+ A1.H, R3 = A0.L \+ A0.H;
-[ 0-9a-f]+:    0c c4 00 4b     R4 = A1.L \+ A1.H, R5 = A0.L \+ A0.H;
-[ 0-9a-f]+:    0c c4 80 4f     R6 = A1.L \+ A1.H, R7 = A0.L \+ A0.H;
+[ 0-9a-f]+:    0c c4 3f 42     R0 = A1.L \+ A1.H, R1 = A0.L \+ A0.H;
+[ 0-9a-f]+:    0c c4 bf 46     R2 = A1.L \+ A1.H, R3 = A0.L \+ A0.H;
+[ 0-9a-f]+:    0c c4 3f 4b     R4 = A1.L \+ A1.H, R5 = A0.L \+ A0.H;
+[ 0-9a-f]+:    0c c4 bf 4f     R6 = A1.L \+ A1.H, R7 = A0.L \+ A0.H;
 [ 0-9a-f]+:    15 c4 d0 01     \(R7, R0\) = BYTEOP16P \(R3:2, R1:0\);
 [ 0-9a-f]+:    15 c4 50 04     \(R1, R2\) = BYTEOP16P \(R3:2, R1:0\);
 [ 0-9a-f]+:    15 c4 10 02     \(R0, R1\) = BYTEOP16P \(R3:2, R1:0\);

Attachment: upstream.patch
Description: upstream.patch

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