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PATCH: Implement BMI instructions
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: binutils at sourceware dot org
- Date: Tue, 4 Jan 2011 16:18:20 -0800
- Subject: PATCH: Implement BMI instructions
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
I checked in this patch to implement BMI instructions.
H.J.
---
gas/
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Allow encoding 32/64bit
integer registers in VEX.vvvv. Check register-only source
operand when two source operands are swapped. Properly update
destination when two source operands are swapped.
gas/testsuite/
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/bmi-intel.d: New.
* gas/i386/bmi.d: Likewise.
* gas/i386/bmi.s: Likewise.
* gas/i386/x86-64-bmi-intel.d: Likewise.
* gas/i386/x86-64-bmi.d: Likewise.
* gas/i386/x86-64-bmi.s: Likewise.
* gas/i386/i386.exp: Run bmi, bmi-intel, x86-64-bmi and
x86-64-bmi-intel.
opcodes/
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (REG_VEX_38F3): New.
(PREFIX_0FBC): Likewise.
(PREFIX_VEX_38F2): Likewise.
(PREFIX_VEX_38F3_REG_1): Likewise.
(PREFIX_VEX_38F3_REG_2): Likewise.
(PREFIX_VEX_38F3_REG_3): Likewise.
(PREFIX_VEX_38F7): Likewise.
(VEX_LEN_38F2_P_0): Likewise.
(VEX_LEN_38F3_R_1_P_0): Likewise.
(VEX_LEN_38F3_R_2_P_0): Likewise.
(VEX_LEN_38F3_R_3_P_0): Likewise.
(VEX_LEN_38F7_P_0): Likewise.
(dis386_twobyte): Use PREFIX_0FBC.
(reg_table): Add REG_VEX_38F3.
(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
PREFIX_VEX_38F7.
(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
VEX_LEN_38F7_P_0.
* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
(cpu_flags): Add CpuBMI.
* i386-opc.h (CpuBMI): New.
(i386_cpu_flags): Add cpubmi.
* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 7ca97a6..2e28d8e 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5310,16 +5310,34 @@ build_modrm_byte (void)
if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
{
/* For instructions with VexNDS, the register-only
- source operand must be XMM or YMM register. It is
- encoded in VEX prefix. We need to clear RegMem bit
- before calling operand_type_equal. */
- i386_operand_type op = i.tm.operand_types[dest];
+ source operand must be 32/64bit integer, XMM or
+ YMM register. It is encoded in VEX prefix. We
+ need to clear RegMem bit before calling
+ operand_type_equal. */
+
+ i386_operand_type op;
+ unsigned int vvvv;
+
+ /* Check register-only source operand when two source
+ operands are swapped. */
+ if (!i.tm.operand_types[source].bitfield.baseindex
+ && i.tm.operand_types[dest].bitfield.baseindex)
+ {
+ vvvv = source;
+ source = dest;
+ }
+ else
+ vvvv = dest;
+
+ op = i.tm.operand_types[vvvv];
op.bitfield.regmem = 0;
if ((dest + 1) >= i.operands
- || (!operand_type_equal (&op, ®xmm)
+ || (op.bitfield.reg32 != 1
+ && !op.bitfield.reg64 != 1
+ && !operand_type_equal (&op, ®xmm)
&& !operand_type_equal (&op, ®ymm)))
abort ();
- i.vex.register_specifier = i.op[dest].regs;
+ i.vex.register_specifier = i.op[vvvv].regs;
dest++;
}
}
@@ -5647,30 +5665,51 @@ build_modrm_byte (void)
}
else
{
- vex_reg = op + 1;
- gas_assert (vex_reg < i.operands);
+ /* Check register-only source operand when two source
+ operands are swapped. */
+ if (!i.tm.operand_types[op].bitfield.baseindex
+ && i.tm.operand_types[op + 1].bitfield.baseindex)
+ {
+ vex_reg = op;
+ op += 2;
+ gas_assert (mem == (vex_reg + 1)
+ && op < i.operands);
+ }
+ else
+ {
+ vex_reg = op + 1;
+ gas_assert (vex_reg < i.operands);
+ }
}
}
else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
{
- /* For instructions with VexNDD, there should be
- no memory operand and the register destination
+ /* For instructions with VexNDD, the register destination
is encoded in VEX prefix. */
- gas_assert (i.mem_operands == 0
- && (op + 2) == i.operands);
- vex_reg = op + 1;
+ if (i.mem_operands == 0)
+ {
+ /* There is no memory operand. */
+ gas_assert ((op + 2) == i.operands);
+ vex_reg = op + 1;
+ }
+ else
+ {
+ /* There are only 2 operands. */
+ gas_assert (op < 2 && i.operands == 2);
+ vex_reg = 1;
+ }
}
else
gas_assert (op < i.operands);
if (vex_reg != (unsigned int) ~0)
{
- gas_assert (i.reg_operands == 2);
+ i386_operand_type *type = &i.tm.operand_types[vex_reg];
- if (!operand_type_equal (&i.tm.operand_types[vex_reg],
- ®xmm)
- && !operand_type_equal (&i.tm.operand_types[vex_reg],
- ®ymm))
+ if (type->bitfield.reg32 != 1
+ && type->bitfield.reg64 != 1
+ && !operand_type_equal (type, ®xmm)
+ && !operand_type_equal (type, ®ymm))
abort ();
i.vex.register_specifier = i.op[vex_reg].regs;
diff --git a/gas/testsuite/gas/i386/bmi-intel.d b/gas/testsuite/gas/i386/bmi-intel.d
new file mode 100644
index 0000000..38eb5b4
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi-intel.d
@@ -0,0 +1,47 @@
+#as:
+#objdump: -dwMintel
+#name: i386 BMI insns (Intel disassembly)
+#source: bmi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt bx,ax
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt bx,WORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr esi,DWORD PTR \[ecx\],ebx
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt ebx,eax
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt bx,ax
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt bx,WORD PTR \[ecx\]
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt bx,WORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr esi,DWORD PTR \[ecx\],ebx
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr esi,DWORD PTR \[ecx\],ebx
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt ebx,eax
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr ebx,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr ebx,DWORD PTR \[ecx\]
+#pass
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
new file mode 100644
index 0000000..1cded8b
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.d
@@ -0,0 +1,46 @@
+#as:
+#objdump: -dw
+#name: i386 BMI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %ax,%bx
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt \(%ecx\),%bx
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %eax,%ebx
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr \(%ecx\),%ebx
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %ax,%bx
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt \(%ecx\),%bx
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt \(%ecx\),%bx
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %eax,%ebx
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt \(%ecx\),%ebx
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr \(%ecx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr \(%ecx\),%ebx
+#pass
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
new file mode 100644
index 0000000..fe22145
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.s
@@ -0,0 +1,58 @@
+# Check 32bit BMI instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+# Test for op r16, r/m16
+ tzcnt %ax,%bx
+ tzcnt (%ecx),%bx
+
+# Test for op r32, r32, r/m32
+ andn %eax,%ebx,%esi
+ andn (%ecx),%ebx,%esi
+
+# Test for op r32, r/m32, r32
+ bextr %eax,%ebx,%esi
+ bextr %ebx,(%ecx),%esi
+
+# Test for op r32, r/m32
+ tzcnt %eax,%ebx
+ tzcnt (%ecx),%ebx
+ blsi %eax,%ebx
+ blsi (%ecx),%ebx
+ blsmsk %eax,%ebx
+ blsmsk (%ecx),%ebx
+ blsr %eax,%ebx
+ blsr (%ecx),%ebx
+
+ .intel_syntax noprefix
+
+# Test for op r16, r/m16
+ tzcnt bx,ax
+ tzcnt bx,WORD PTR [ecx]
+ tzcnt bx,[ecx]
+
+# Test for op r32, r32, r/m32
+ andn esi,ebx,eax
+ andn esi,ebx,DWORD PTR [ecx]
+ andn esi,ebx,[ecx]
+
+# Test for op r32, r/m32, r32
+ bextr esi,ebx,eax
+ bextr esi,DWORD PTR [ecx],ebx
+ bextr esi,[ecx],ebx
+
+# Test for op r32, r/m32
+ tzcnt ebx,eax
+ tzcnt ebx,DWORD PTR [ecx]
+ tzcnt ebx,[ecx]
+ blsi ebx,eax
+ blsi ebx,DWORD PTR [ecx]
+ blsi ebx,[ecx]
+ blsmsk ebx,eax
+ blsmsk ebx,DWORD PTR [ecx]
+ blsmsk ebx,[ecx]
+ blsr ebx,eax
+ blsr ebx,DWORD PTR [ecx]
+ blsr ebx,[ecx]
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a966d7..2d36fae 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "fma4"
run_dump_test "lwp"
run_dump_test "xop"
+ run_dump_test "bmi"
+ run_dump_test "bmi-intel"
run_dump_test "f16c"
run_dump_test "f16c-intel"
run_dump_test "fsgs"
@@ -372,6 +374,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-fma4"
run_dump_test "x86-64-lwp"
run_dump_test "x86-64-xop"
+ run_dump_test "x86-64-bmi"
+ run_dump_test "x86-64-bmi-intel"
run_dump_test "x86-64-f16c"
run_dump_test "x86-64-f16c-intel"
run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/x86-64-bmi-intel.d b/gas/testsuite/gas/i386/x86-64-bmi-intel.d
new file mode 100644
index 0000000..09cfa00
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi-intel.d
@@ -0,0 +1,119 @@
+#as:
+#objdump: -dwMintel
+#name: x86-64 BMI insns (Intel disassembly)
+#source: x86-64-bmi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt bx,ax
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt bx,WORD PTR \[rcx\]
+[ ]*[a-f0-9]+: 66 f3 44 0f bc 39 tzcnt r15w,WORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 42 00 f2 d1 andn r10d,r15d,r9d
+[ ]*[a-f0-9]+: c4 62 00 f2 11 andn r10d,r15d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr esi,DWORD PTR \[rcx\],ebx
+[ ]*[a-f0-9]+: c4 42 30 f7 d7 bextr r10d,r15d,r9d
+[ ]*[a-f0-9]+: c4 62 30 f7 11 bextr r10d,DWORD PTR \[rcx\],r9d
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt ebx,eax
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: f3 44 0f bc 39 tzcnt r15d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 00 f3 19 blsi r15d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 00 f3 11 blsmsk r15d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 00 f3 09 blsr r15d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn rsi,rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn rsi,rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 42 80 f2 d1 andn r10,r15,r9
+[ ]*[a-f0-9]+: c4 62 80 f2 11 andn r10,r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 f8 f7 f3 bextr rsi,rbx,rax
+[ ]*[a-f0-9]+: c4 e2 f8 f7 31 bextr rsi,QWORD PTR \[rcx\],rax
+[ ]*[a-f0-9]+: c4 42 b0 f7 d7 bextr r10,r15,r9
+[ ]*[a-f0-9]+: c4 62 b0 f7 11 bextr r10,QWORD PTR \[rcx\],r9
+[ ]*[a-f0-9]+: f3 48 0f bc d8 tzcnt rbx,rax
+[ ]*[a-f0-9]+: f3 48 0f bc 19 tzcnt rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: f3 4d 0f bc f9 tzcnt r15,r9
+[ ]*[a-f0-9]+: f3 4c 0f bc 39 tzcnt r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d8 blsi rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 c2 80 f3 d9 blsi r15,r9
+[ ]*[a-f0-9]+: c4 e2 80 f3 19 blsi r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d0 blsmsk rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 c2 80 f3 d1 blsmsk r15,r9
+[ ]*[a-f0-9]+: c4 e2 80 f3 11 blsmsk r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 c8 blsr rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 c2 80 f3 c9 blsr r15,r9
+[ ]*[a-f0-9]+: c4 e2 80 f3 09 blsr r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt bx,ax
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt bx,WORD PTR \[rcx\]
+[ ]*[a-f0-9]+: 66 f3 44 0f bc 11 tzcnt r10w,WORD PTR \[rcx\]
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt bx,WORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 42 28 f2 f9 andn r15d,r10d,r9d
+[ ]*[a-f0-9]+: c4 62 28 f2 39 andn r15d,r10d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr esi,ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr esi,DWORD PTR \[rcx\],ebx
+[ ]*[a-f0-9]+: c4 42 30 f7 fa bextr r15d,r10d,r9d
+[ ]*[a-f0-9]+: c4 62 30 f7 39 bextr r15d,DWORD PTR \[rcx\],r9d
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr esi,DWORD PTR \[rcx\],ebx
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt ebx,eax
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: f3 44 0f bc 11 tzcnt r10d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 28 f3 19 blsi r10d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 28 f3 11 blsmsk r10d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr ebx,eax
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 28 f3 09 blsr r10d,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr ebx,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn rsi,rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn rsi,rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 42 80 f2 d1 andn r10,r15,r9
+[ ]*[a-f0-9]+: c4 62 80 f2 11 andn r10,r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn rsi,rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 f8 f7 f3 bextr rsi,rbx,rax
+[ ]*[a-f0-9]+: c4 e2 f8 f7 31 bextr rsi,QWORD PTR \[rcx\],rax
+[ ]*[a-f0-9]+: c4 42 b0 f7 d7 bextr r10,r15,r9
+[ ]*[a-f0-9]+: c4 62 b0 f7 11 bextr r10,QWORD PTR \[rcx\],r9
+[ ]*[a-f0-9]+: c4 e2 f8 f7 31 bextr rsi,QWORD PTR \[rcx\],rax
+[ ]*[a-f0-9]+: f3 48 0f bc d8 tzcnt rbx,rax
+[ ]*[a-f0-9]+: f3 48 0f bc 19 tzcnt rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: f3 4d 0f bc f9 tzcnt r15,r9
+[ ]*[a-f0-9]+: f3 4c 0f bc 39 tzcnt r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: f3 48 0f bc 19 tzcnt rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d8 blsi rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 c2 80 f3 d9 blsi r15,r9
+[ ]*[a-f0-9]+: c4 e2 80 f3 19 blsi r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d0 blsmsk rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 c2 80 f3 d1 blsmsk r15,r9
+[ ]*[a-f0-9]+: c4 e2 80 f3 11 blsmsk r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 c8 blsr rbx,rax
+[ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr rbx,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 c2 80 f3 c9 blsr r15,r9
+[ ]*[a-f0-9]+: c4 e2 80 f3 09 blsr r15,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr rbx,QWORD PTR \[rcx\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
new file mode 100644
index 0000000..9b59d10
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.d
@@ -0,0 +1,118 @@
+#as:
+#objdump: -dw
+#name: x86-64 BMI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %ax,%bx
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt \(%rcx\),%bx
+[ ]*[a-f0-9]+: 66 f3 44 0f bc 39 tzcnt \(%rcx\),%r15w
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%rcx\),%ebx,%esi
+[ ]*[a-f0-9]+: c4 42 00 f2 d1 andn %r9d,%r15d,%r10d
+[ ]*[a-f0-9]+: c4 62 00 f2 11 andn \(%rcx\),%r15d,%r10d
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr %ebx,\(%rcx\),%esi
+[ ]*[a-f0-9]+: c4 42 30 f7 d7 bextr %r9d,%r15d,%r10d
+[ ]*[a-f0-9]+: c4 62 30 f7 11 bextr %r9d,\(%rcx\),%r10d
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %eax,%ebx
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt \(%rcx\),%ebx
+[ ]*[a-f0-9]+: f3 44 0f bc 39 tzcnt \(%rcx\),%r15d
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 00 f3 19 blsi \(%rcx\),%r15d
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 00 f3 11 blsmsk \(%rcx\),%r15d
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 00 f3 09 blsr \(%rcx\),%r15d
+[ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn %rax,%rbx,%rsi
+[ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn \(%rcx\),%rbx,%rsi
+[ ]*[a-f0-9]+: c4 42 80 f2 d1 andn %r9,%r15,%r10
+[ ]*[a-f0-9]+: c4 62 80 f2 11 andn \(%rcx\),%r15,%r10
+[ ]*[a-f0-9]+: c4 e2 f8 f7 f3 bextr %rax,%rbx,%rsi
+[ ]*[a-f0-9]+: c4 e2 f8 f7 31 bextr %rax,\(%rcx\),%rsi
+[ ]*[a-f0-9]+: c4 42 b0 f7 d7 bextr %r9,%r15,%r10
+[ ]*[a-f0-9]+: c4 62 b0 f7 11 bextr %r9,\(%rcx\),%r10
+[ ]*[a-f0-9]+: f3 48 0f bc d8 tzcnt %rax,%rbx
+[ ]*[a-f0-9]+: f3 48 0f bc 19 tzcnt \(%rcx\),%rbx
+[ ]*[a-f0-9]+: f3 4d 0f bc f9 tzcnt %r9,%r15
+[ ]*[a-f0-9]+: f3 4c 0f bc 39 tzcnt \(%rcx\),%r15
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d8 blsi %rax,%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 c2 80 f3 d9 blsi %r9,%r15
+[ ]*[a-f0-9]+: c4 e2 80 f3 19 blsi \(%rcx\),%r15
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d0 blsmsk %rax,%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 c2 80 f3 d1 blsmsk %r9,%r15
+[ ]*[a-f0-9]+: c4 e2 80 f3 11 blsmsk \(%rcx\),%r15
+[ ]*[a-f0-9]+: c4 e2 e0 f3 c8 blsr %rax,%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 c2 80 f3 c9 blsr %r9,%r15
+[ ]*[a-f0-9]+: c4 e2 80 f3 09 blsr \(%rcx\),%r15
+[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %ax,%bx
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt \(%rcx\),%bx
+[ ]*[a-f0-9]+: 66 f3 44 0f bc 11 tzcnt \(%rcx\),%r10w
+[ ]*[a-f0-9]+: 66 f3 0f bc 19 tzcnt \(%rcx\),%bx
+[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%rcx\),%ebx,%esi
+[ ]*[a-f0-9]+: c4 42 28 f2 f9 andn %r9d,%r10d,%r15d
+[ ]*[a-f0-9]+: c4 62 28 f2 39 andn \(%rcx\),%r10d,%r15d
+[ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%rcx\),%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr %ebx,\(%rcx\),%esi
+[ ]*[a-f0-9]+: c4 42 30 f7 fa bextr %r9d,%r10d,%r15d
+[ ]*[a-f0-9]+: c4 62 30 f7 39 bextr %r9d,\(%rcx\),%r15d
+[ ]*[a-f0-9]+: c4 e2 60 f7 31 bextr %ebx,\(%rcx\),%esi
+[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %eax,%ebx
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt \(%rcx\),%ebx
+[ ]*[a-f0-9]+: f3 44 0f bc 11 tzcnt \(%rcx\),%r10d
+[ ]*[a-f0-9]+: f3 0f bc 19 tzcnt \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 28 f3 19 blsi \(%rcx\),%r10d
+[ ]*[a-f0-9]+: c4 e2 60 f3 19 blsi \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 28 f3 11 blsmsk \(%rcx\),%r10d
+[ ]*[a-f0-9]+: c4 e2 60 f3 11 blsmsk \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 28 f3 09 blsr \(%rcx\),%r10d
+[ ]*[a-f0-9]+: c4 e2 60 f3 09 blsr \(%rcx\),%ebx
+[ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn %rax,%rbx,%rsi
+[ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn \(%rcx\),%rbx,%rsi
+[ ]*[a-f0-9]+: c4 42 80 f2 d1 andn %r9,%r15,%r10
+[ ]*[a-f0-9]+: c4 62 80 f2 11 andn \(%rcx\),%r15,%r10
+[ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn \(%rcx\),%rbx,%rsi
+[ ]*[a-f0-9]+: c4 e2 f8 f7 f3 bextr %rax,%rbx,%rsi
+[ ]*[a-f0-9]+: c4 e2 f8 f7 31 bextr %rax,\(%rcx\),%rsi
+[ ]*[a-f0-9]+: c4 42 b0 f7 d7 bextr %r9,%r15,%r10
+[ ]*[a-f0-9]+: c4 62 b0 f7 11 bextr %r9,\(%rcx\),%r10
+[ ]*[a-f0-9]+: c4 e2 f8 f7 31 bextr %rax,\(%rcx\),%rsi
+[ ]*[a-f0-9]+: f3 48 0f bc d8 tzcnt %rax,%rbx
+[ ]*[a-f0-9]+: f3 48 0f bc 19 tzcnt \(%rcx\),%rbx
+[ ]*[a-f0-9]+: f3 4d 0f bc f9 tzcnt %r9,%r15
+[ ]*[a-f0-9]+: f3 4c 0f bc 39 tzcnt \(%rcx\),%r15
+[ ]*[a-f0-9]+: f3 48 0f bc 19 tzcnt \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d8 blsi %rax,%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 c2 80 f3 d9 blsi %r9,%r15
+[ ]*[a-f0-9]+: c4 e2 80 f3 19 blsi \(%rcx\),%r15
+[ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 d0 blsmsk %rax,%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 c2 80 f3 d1 blsmsk %r9,%r15
+[ ]*[a-f0-9]+: c4 e2 80 f3 11 blsmsk \(%rcx\),%r15
+[ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 c8 blsr %rax,%rbx
+[ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr \(%rcx\),%rbx
+[ ]*[a-f0-9]+: c4 c2 80 f3 c9 blsr %r9,%r15
+[ ]*[a-f0-9]+: c4 e2 80 f3 09 blsr \(%rcx\),%r15
+[ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr \(%rcx\),%rbx
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
new file mode 100644
index 0000000..ef222c9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.s
@@ -0,0 +1,142 @@
+# Check 64bit BMI instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+# Test for op r16, r/m16
+ tzcnt %ax,%bx
+ tzcnt (%rcx),%bx
+ tzcnt (%rcx),%r15w
+
+# Test for op r32, r32, r/m32
+ andn %eax,%ebx,%esi
+ andn (%rcx),%ebx,%esi
+ andn %r9d,%r15d,%r10d
+ andn (%rcx),%r15d,%r10d
+
+# Test for op r32, r/m32, r32
+ bextr %eax,%ebx,%esi
+ bextr %ebx,(%rcx),%esi
+ bextr %r9d,%r15d,%r10d
+ bextr %r9d,(%rcx),%r10d
+
+# Test for op r32, r/m32
+ tzcnt %eax,%ebx
+ tzcnt (%rcx),%ebx
+ tzcnt (%rcx),%r15d
+ blsi %eax,%ebx
+ blsi (%rcx),%ebx
+ blsi (%rcx),%r15d
+ blsmsk %eax,%ebx
+ blsmsk (%rcx),%ebx
+ blsmsk (%rcx),%r15d
+ blsr %eax,%ebx
+ blsr (%rcx),%ebx
+ blsr (%rcx),%r15d
+
+# Test for op r64, r64, r/m64
+ andn %rax,%rbx,%rsi
+ andn (%rcx),%rbx,%rsi
+ andn %r9,%r15,%r10
+ andn (%rcx),%r15,%r10
+
+# Test for op r64, r/m64, r64
+ bextr %rax,%rbx,%rsi
+ bextr %rax,(%rcx),%rsi
+ bextr %r9,%r15,%r10
+ bextr %r9,(%rcx),%r10
+
+# Test for op r64, r/m64
+ tzcnt %rax,%rbx
+ tzcnt (%rcx),%rbx
+ tzcnt %r9,%r15
+ tzcnt (%rcx),%r15
+ blsi %rax,%rbx
+ blsi (%rcx),%rbx
+ blsi %r9,%r15
+ blsi (%rcx),%r15
+ blsmsk %rax,%rbx
+ blsmsk (%rcx),%rbx
+ blsmsk %r9,%r15
+ blsmsk (%rcx),%r15
+ blsr %rax,%rbx
+ blsr (%rcx),%rbx
+ blsr %r9,%r15
+ blsr (%rcx),%r15
+
+ .intel_syntax noprefix
+
+# Test for op r16, r/m16
+ tzcnt bx,ax
+ tzcnt bx,WORD PTR [rcx]
+ tzcnt r10w,WORD PTR [rcx]
+ tzcnt bx,[rcx]
+
+# Test for op r32, r32, r/m32
+ andn esi,ebx,eax
+ andn esi,ebx,DWORD PTR [rcx]
+ andn r15d,r10d,r9d
+ andn r15d,r10d,DWORD PTR [rcx]
+ andn esi,ebx,[rcx]
+
+# Test for op r32, r/m32, r32
+ bextr esi,ebx,eax
+ bextr esi,DWORD PTR [rcx],ebx
+ bextr r15d,r10d,r9d
+ bextr r15d,DWORD PTR [rcx],r9d
+ bextr esi,[rcx],ebx
+
+# Test for op r32, r/m32
+ tzcnt ebx,eax
+ tzcnt ebx,DWORD PTR [rcx]
+ tzcnt r10d,DWORD PTR [rcx]
+ tzcnt ebx,[rcx]
+ blsi ebx,eax
+ blsi ebx,DWORD PTR [rcx]
+ blsi r10d,DWORD PTR [rcx]
+ blsi ebx,[rcx]
+ blsmsk ebx,eax
+ blsmsk ebx,DWORD PTR [rcx]
+ blsmsk r10d,DWORD PTR [rcx]
+ blsmsk ebx,[rcx]
+ blsr ebx,eax
+ blsr ebx,DWORD PTR [rcx]
+ blsr r10d,DWORD PTR [rcx]
+ blsr ebx,[rcx]
+
+# Test for op r64, r64, r/m64
+ andn rsi,rbx,rax
+ andn rsi,rbx,QWORD PTR [rcx]
+ andn r10,r15,r9
+ andn r10,r15,QWORD PTR [rcx]
+ andn rsi,rbx,[rcx]
+
+# Test for op r64, r/m64, r64
+ bextr rsi,rbx,rax
+ bextr rsi,QWORD PTR [rcx],rax
+ bextr r10,r15,r9
+ bextr r10,QWORD PTR [rcx],r9
+ bextr rsi,[rcx],rax
+
+# Test for op r64, r/m64
+ tzcnt rbx,rax
+ tzcnt rbx,QWORD PTR [rcx]
+ tzcnt r15,r9
+ tzcnt r15,QWORD PTR [rcx]
+ tzcnt rbx,[rcx]
+ blsi rbx,rax
+ blsi rbx,QWORD PTR [rcx]
+ blsi r15,r9
+ blsi r15,QWORD PTR [rcx]
+ blsi rbx,[rcx]
+ blsmsk rbx,rax
+ blsmsk rbx,QWORD PTR [rcx]
+ blsmsk r15,r9
+ blsmsk r15,QWORD PTR [rcx]
+ blsmsk rbx,[rcx]
+ blsr rbx,rax
+ blsr rbx,QWORD PTR [rcx]
+ blsr r15,r9
+ blsr r15,QWORD PTR [rcx]
+ blsr rbx,[rcx]
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index d1482de..9e18bac 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -599,6 +599,7 @@ enum
REG_VEX_0F72,
REG_VEX_0F73,
REG_VEX_0FAE,
+ REG_VEX_0F38F3,
REG_XOP_LWPCB,
REG_XOP_LWP
};
@@ -747,6 +748,7 @@ enum
PREFIX_0FAE_REG_2,
PREFIX_0FAE_REG_3,
PREFIX_0FB8,
+ PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0FC2,
PREFIX_0FC3,
@@ -1015,6 +1017,11 @@ enum
PREFIX_VEX_0F38DD,
PREFIX_VEX_0F38DE,
PREFIX_VEX_0F38DF,
+ PREFIX_VEX_0F38F2,
+ PREFIX_VEX_0F38F3_REG_1,
+ PREFIX_VEX_0F38F3_REG_2,
+ PREFIX_VEX_0F38F3_REG_3,
+ PREFIX_VEX_0F38F7,
PREFIX_VEX_0F3A04,
PREFIX_VEX_0F3A05,
PREFIX_VEX_0F3A06,
@@ -1298,6 +1305,11 @@ enum
VEX_LEN_0F38DD_P_2,
VEX_LEN_0F38DE_P_2,
VEX_LEN_0F38DF_P_2,
+ VEX_LEN_0F38F2_P_0,
+ VEX_LEN_0F38F3_R_1_P_0,
+ VEX_LEN_0F38F3_R_2_P_0,
+ VEX_LEN_0F38F3_R_3_P_0,
+ VEX_LEN_0F38F7_P_0,
VEX_LEN_0F3A06_P_2,
VEX_LEN_0F3A0A_P_2,
VEX_LEN_0F3A0B_P_2,
@@ -2159,7 +2171,7 @@ static const struct dis386 dis386_twobyte[] = {
{ "ud1", { XX } },
{ REG_TABLE (REG_0FBA) },
{ "btcS", { Ev, Gv } },
- { "bsfS", { Gv, Ev } },
+ { PREFIX_TABLE (PREFIX_0FBC) },
{ PREFIX_TABLE (PREFIX_0FBD) },
{ "movs{bR|x}", { Gv, Eb } },
{ "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
@@ -2750,6 +2762,13 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_VEX_0FAE_REG_2) },
{ MOD_TABLE (MOD_VEX_0FAE_REG_3) },
},
+ /* REG_VEX_0F38F3 */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
+ },
/* REG_XOP_LWPCB */
{
{ "llwpcb", { { OP_LWPCB_E, 0 } } },
@@ -3070,6 +3089,13 @@ static const struct dis386 prefix_table[][4] = {
{ "popcntS", { Gv, Ev } },
},
+ /* PREFIX_0FBC */
+ {
+ { "bsfS", { Gv, Ev } },
+ { "tzcntS", { Gv, Ev } },
+ { "bsfS", { Gv, Ev } },
+ },
+
/* PREFIX_0FBD */
{
{ "bsrS", { Gv, Ev } },
@@ -4969,6 +4995,31 @@ static const struct dis386 prefix_table[][4] = {
{ VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
},
+ /* PREFIX_VEX_0F38F2 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_1 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_2 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_3 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F7 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
+ },
+
/* PREFIX_VEX_0F3A04 */
{
{ Bad_Opcode },
@@ -7829,12 +7880,12 @@ static const struct dis386 vex_table[][256] = {
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
+ { REG_TABLE (REG_VEX_0F38F3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
/* f8 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -9034,6 +9085,31 @@ static const struct dis386 vex_len_table[][2] = {
{ VEX_W_TABLE (VEX_W_0F38DF_P_2) },
},
+ /* VEX_LEN_0F38F2_P_0 */
+ {
+ { "andnS", { Gdq, VexGdq, Edq } },
+ },
+
+ /* VEX_LEN_0F38F3_R_1_P_0 */
+ {
+ { "blsrS", { VexGdq, Edq } },
+ },
+
+ /* VEX_LEN_0F38F3_R_2_P_0 */
+ {
+ { "blsmskS", { VexGdq, Edq } },
+ },
+
+ /* VEX_LEN_0F38F3_R_3_P_0 */
+ {
+ { "blsiS", { VexGdq, Edq } },
+ },
+
+ /* VEX_LEN_0F38F7_P_0 */
+ {
+ { "bextrS", { Gdq, Edq, VexGdq } },
+ },
+
/* VEX_LEN_0F3A06_P_2 */
{
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 81e51dd..4b2ed29 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,6 +140,8 @@ static initializer cpu_flag_init[] =
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
{ "CPU_LWP_FLAGS",
"CpuLWP" },
+ { "CPU_BMI_FLAGS",
+ "CpuBMI" },
{ "CPU_MOVBE_FLAGS",
"CpuMovbe" },
{ "CPU_RDTSCP_FLAGS",
@@ -320,6 +322,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuFMA4),
BITFIELD (CpuXOP),
BITFIELD (CpuLWP),
+ BITFIELD (CpuBMI),
BITFIELD (CpuLM),
BITFIELD (CpuMovbe),
BITFIELD (CpuEPT),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index fe4fe97..6696983 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,6 +110,8 @@ enum
CpuXOP,
/* LWP support required */
CpuLWP,
+ /* BMI support required */
+ CpuBMI,
/* MOVBE Instruction support required */
CpuMovbe,
/* EPT Instructions required */
@@ -186,6 +188,7 @@ typedef union i386_cpu_flags
unsigned int cpufma4:1;
unsigned int cpuxop:1;
unsigned int cpulwp:1;
+ unsigned int cpubmi:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f63919e..84fb818 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,6 +2733,15 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+// BMI instructions
+
+andn, 3, 0xf2, None, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64, Reg32|Reg64 }
+bextr, 3, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
+blsi, 2, 0xf3, 0x3, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
+blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
+blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
+tzcnt, 2, 0xf30fbc, None, 2, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+
// AMD 3DNow! instructions.
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }