This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: [PATCH MIPS][LS3A]Generic Support
Hi Maciej,
My apologies for approving Mingming's patch without checking through
your objections first.
I think that the placement of the loongson_3a entry in the elfxx-mips.c
and tc-mips.c is not really that important, so I am inclined to let the
patch stand as it is. But your objections to the include/opcodes/mips.h
patch is valid:
> #define INSN_LOONGSON_2F 0x80000000
> +/* Loongson 3A. */
> +#define INSN_LOONGSON_3A 0x80000400
> /* RMI Xlr instruction */
> #define INSN_XLR 0x00000020
one bit per CPU type and you need to update INSN_CHIP_MASK accordingly.
How about this fix to correct the problem:
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.68
diff -u -3 -p -r1.68 mips.h
--- include/opcode/mips.h 11 Nov 2010 10:23:38 -0000 1.68
+++ include/opcode/mips.h 19 Nov 2010 16:43:22 -0000
@@ -556,8 +556,6 @@ static const unsigned int mips_isa_table
#define INSN_DSP 0x00001000
#define INSN_DSP64 0x00002000
-/* 0x00004000 is unused. */
-
/* MIPS-3D ASE */
#define INSN_MIPS3D 0x00008000
@@ -595,7 +593,8 @@ static const unsigned int mips_isa_table
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
/* Loongson 3A. */
-#define INSN_LOONGSON_3A 0x80000400
+#define INSN_LOONGSON_3A 0x00004000
+
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
Ie making use of the one unused bit in the mask. Of course this does
mean that next time a new MIPS architecture is added, this whole problem
is going to have to be revisited.
Cheers
Nick