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Re: [PATCH MIPS][LS3A]Generic Support
- From: "Maciej W. Rozycki" <macro at linux-mips dot org>
- To: Mingming Sun <mingm dot sun at gmail dot com>
- Cc: Nick Clifton <nickc at redhat dot com>, binutils <binutils at sourceware dot org>
- Date: Wed, 10 Nov 2010 23:27:24 +0000 (GMT)
- Subject: Re: [PATCH MIPS][LS3A]Generic Support
- References: <8762xu164h.fsf@firetop.home> <4CA0943D.4000407@redhat.com> <AANLkTinAhg2YwLhgSO2Vd8zE2zhEpsLbZzduztepxniw@mail.gmail.com>
On Wed, 10 Nov 2010, Mingming Sun wrote:
> I've got the binutils FSF copyright assignment recently.
> Is this patch ok for binutils?
Overall it looks OK to me, but I cannot approve the change, though I can
make objections. ;) A couple of comments follow.
First I think your new entry should be placed after one for the SB-1A.
Specifically here:
> Index: bfd/elfxx-mips.c
> ===================================================================
> RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
> retrieving revision 1.274
> diff -u -p -r1.274 elfxx-mips.c
> --- bfd/elfxx-mips.c 19 Sep 2010 10:52:17 -0000 1.274
> +++ bfd/elfxx-mips.c 21 Sep 2010 08:52:49 -0000
> @@ -10561,6 +10564,10 @@ mips_set_isa_flags (bfd *abfd)
> val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
> break;
>
> + case bfd_mach_mips_loongson_3a:
> + val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
> + break;
> +
> case bfd_mach_mips_sb1:
> val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
> break;
and here:
> Index: gas/config/tc-mips.c
> ===================================================================
> RCS file: /cvs/src/src/gas/config/tc-mips.c,v
> retrieving revision 1.425
> diff -u -p -r1.425 tc-mips.c
> --- gas/config/tc-mips.c 27 Jul 2010 21:04:59 -0000 1.425
> +++ gas/config/tc-mips.c 21 Sep 2010 08:53:08 -0000
> @@ -15383,6 +15383,7 @@ static const struct mips_cpu_info mips_c
> { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
> { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
> { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
> + { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
>
> /* Broadcom SB-1 CPU core */
> { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
Then:
> Index: include/opcode/mips.h
> ===================================================================
> RCS file: /cvs/src/src/include/opcode/mips.h,v
> retrieving revision 1.67
> diff -u -p -r1.67 mips.h
> --- include/opcode/mips.h 6 Jul 2010 00:02:44 -0000 1.67
> +++ include/opcode/mips.h 21 Sep 2010 08:53:11 -0000
> @@ -594,6 +594,8 @@ static const unsigned int mips_isa_table
> #define INSN_LOONGSON_2E 0x40000000
> /* ST Microelectronics Loongson 2F. */
> #define INSN_LOONGSON_2F 0x80000000
> +/* Loongson 3A. */
> +#define INSN_LOONGSON_3A 0x80000400
> /* RMI Xlr instruction */
> #define INSN_XLR 0x00000020
>
one bit per CPU type and you need to update INSN_CHIP_MASK accordingly.
Maciej