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Re: PATCH: PR 658: i386 assembler and disassembler can't handle SIB with INDEX==4
- From: "Jan Beulich" <jbeulich at novell dot com>
- To: "H.J. Lu" <hjl at lucon dot org>
- Cc: <binutils at sourceware dot org>
- Date: Thu, 20 Sep 2007 08:10:21 +0100
- Subject: Re: PATCH: PR 658: i386 assembler and disassembler can't handle SIB with INDEX==4
- References: <46F01045.76E4.0078.0@novell.com> <20070918161747.GA17403@lucon.org> <46F0E118.76E4.0078.0@novell.com> <20070919133853.GA29522@lucon.org> <46F144B5.76E4.0078.0@novell.com> <20070919135120.GA29621@lucon.org> <46F14ADC.76E4.0078.0@novell.com> <20070919141928.GA10114@lucon.org> <46F14DAB.76E4.0078.0@novell.com> <20070919230637.GA14874@lucon.org> <20070920011115.GA15873@lucon.org>
>> It turns out that Intel assembler uses EIZ/RIZ as fake index
>> registers for this purpose. This patch adds a new directive,
>> .allow_index_reg, which will allow EIZ/RIZ as index registers.
>> Are there any comments?
>>
>> Thanks.
>>
>
>Here is the updated patch. It displays EIZ/RIZ only when there
>is an ambiguity. That is "BASE" and "BASE + EIZ/RIZ" have different
>opcodes.
I think that on the assembler end, using %eiz is fine, but on the disassembler
side this pseudo register shouldn't be displayed unless absolutely needed (i.e.
[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
should be
[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,,1\),%esi
or
[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,1\),%esi
depending on what appears to make more sense. Perhaps even more reasonably
we could introduce a new option (or tie this to suffix_always), and by default
retain the old behavior. With the option enabled, you could then of course always
display the fake index.
Jan