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PATCH: S/390: Fix instruction type of efpc and sfpc - take 2
- From: Andreas Krebbel <Andreas dot Krebbel at de dot ibm dot com>
- To: binutils at sourceware dot org
- Cc: schwidefsky at de dot ibm dot com
- Date: Fri, 16 Feb 2007 15:40:20 +0100
- Subject: PATCH: S/390: Fix instruction type of efpc and sfpc - take 2
Hi,
>> the "extract fpc" and "set fpc" instructions take only one register
>> > argument. Fixed with the attached patch.
>> >
>> > OK?
>
>Technically correct but this will break existing applications. In
>particular the glibc won't compile anymore. I'm not sure if we want to
>do that.
So someone indeed added a pointless dummy parameter to glibc inline assembly
instructions instead of fixing a typo in binutils - mmmh.
As you've proposed offline, I've made the extra operand optional so that
now at least the correct versions of the instructions are accepted as well.
objdump still prints efpc and sfpc with the dummy operand. That's a bit
annoying but at least backward compatible.
OK?
-Andreas-
2007-02-16 Andreas Krebbel <krebbel1@de.ibm.com>
* opcodes/s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction
type.
* opcodes/s390-opc.c (s390_operands): Add RO_28 as optional gpr.
(INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc
and sfpc.
Index: opcodes/s390-opc.txt
===================================================================
*** opcodes/s390-opc.txt.orig 2007-02-16 09:49:57.000000000 +0100
--- opcodes/s390-opc.txt 2007-02-16 09:50:38.000000000 +0100
*************** b30d debr RRE_FF "divide short bfp" g5 e
*** 354,360 ****
ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch
b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch
b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch
! b38c efpc RRE_RR "extract fpc" g5 esa,zarch
b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch
b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch
b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch
--- 354,360 ----
ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch
b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch
b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch
! b38c efpc RRE_RR_OPT "extract fpc" g5 esa,zarch
b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch
b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch
b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch
*************** b31f msdbr RRF_F0FF "multiply and subtra
*** 397,403 ****
ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch
b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch
ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch
! b384 sfpc RRE_RR "set fpc" g5 esa,zarch
b299 srnm S_RD "set rounding mode" g5 esa,zarch
b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch
b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch
--- 397,403 ----
ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch
b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch
ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch
! b384 sfpc RRE_RR_OPT "set fpc" g5 esa,zarch
b299 srnm S_RD "set rounding mode" g5 esa,zarch
b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch
b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch
Index: opcodes/s390-opc.c
===================================================================
*** opcodes/s390-opc.c.orig 2007-02-16 09:49:57.000000000 +0100
--- opcodes/s390-opc.c 2007-02-16 15:17:39.000000000 +0100
*************** const struct s390_operand s390_operands[
*** 133,139 ****
#define U32_16 41 /* 32 bit unsigned value starting at 16 */
{ 32, 16, 0 },
#define M_16 42 /* 4 bit optional mask starting at 16 */
! { 4, 16, S390_OPERAND_OPTIONAL }
};
--- 133,142 ----
#define U32_16 41 /* 32 bit unsigned value starting at 16 */
{ 32, 16, 0 },
#define M_16 42 /* 4 bit optional mask starting at 16 */
! { 4, 16, S390_OPERAND_OPTIONAL },
! #define RO_28 43 /* optional GPR starting at position 28 */
! { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }
!
};
*************** const struct s390_operand s390_operands[
*** 202,207 ****
--- 205,213 ----
#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
+ /* Actually efpc and sfpc do not take an optional operand.
+ This is just a workaround for existing code e.g. glibc. */
+ #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
*************** const struct s390_operand s390_operands[
*** 275,280 ****
--- 281,287 ----
#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+ #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }