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Re: [patch] More Thumb2 condexec bugs
- From: Richard Earnshaw <rearnsha at gcc dot gnu dot org>
- To: Paul Brook <paul at codesourcery dot com>
- Cc: binutils at sourceware dot org
- Date: Tue, 09 Aug 2005 09:49:44 +0100
- Subject: Re: [patch] More Thumb2 condexec bugs
- References: <200508082050.11741.paul@codesourcery.com>
On Mon, 2005-08-08 at 20:50, Paul Brook wrote:
> The attached patch fixes some mode thumb2 conditional instruction encodings.
> Specifically the 16-bit forms do not set the condition codes when inside an
> IT block.
>
> Tested on arm-none-eabi.
> Ok?
>
> Paul
> 2005-08-08 Paul Brook <paul@codesourcery.com>
>
> gas/
> * config/tc-arm.c (do_t_mov_cmp): Fix encoding of 16-bit conditional
> instructions.
> (do_t_mvn_tst, do_t_neg, do_t_shift): Ditto.
> gas/testsuite/
> * gas/arm/thumb2_it.s: Add more instruction variants.
> * gas/arm/thumb2_it.d: Ditto.
>
> ______________________________________________________________________
The tc-arm.c changes are fine. However, I'm not particularly keen on
the dump file for the test. For example:
> Index: testsuite/gas/arm/thumb2_it.d
> +0+040 <[^>]+> 0048 lsl.* r0, r1, #1
This patttern would match any amount of random text after the mnemonic
(I think it should really be)
+0+040 <[^>]+> 0048 lsl(eq|s) r0, r1, #1
And ultimately (once the disassembler is fixed) the 's' alternative
should be removed (since this particular insn is conditionally
executed).
R.