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Re: how arm linux to deal with label+offset format!
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Shen Hui <shenhui at arch dot cs dot pku dot edu dot cn>
- Cc: "binutils at sources dot redhat dot com" <binutils at sources dot redhat dot com>, Richard dot Earnshaw at arm dot com
- Date: Mon, 18 Nov 2002 10:15:12 +0000
- Subject: Re: how arm linux to deal with label+offset format!
- Organization: ARM Ltd.
- Reply-to: Richard dot Earnshaw at arm dot com
> I am using binutils-2.10.1,
> if there is a branch instruction whose target address is with format lable+offset, and there also is an pseudo-instruction (for example,adrl)between label and label+offset which need to be expand into more than two instruction , so there may be exists an question.
> but how do deal with it.
>
> for examele:
>
> L1:
> mov r1,r1
> L2:
> b L3+4
> mov r2,r2
> L3: adrl r10,L4
> L4: mov r10,r10
> ... @there may be enougn nop instructions needed to occur an expand in L3
> L5: mov r2,r2
>
>
> as above,
> L2: b L3+4,L3+4 is equal to L4,but when instruction L3:adrl r10,L4 is expand into two instruction(may be: add r10, pc, #immed1;add r10, r10, #immed1), L3+4 not equal L4,so the instruction L2: b L3+4 may branch to an error address.
>
> how to deal with it?
L3+4 means '4 bytes beyond the label L3.' It does not, never has, and
never will mean 'the psuedo instruction after the one at L3.'
So I don't see any problem.
If you are worried about the length of the pseudo instruction adrl then
don't use it. Use adr instead, which is guaranteed to fault if the
addressing range can't be handled by a single instruction.
R.