ABI List

glibc supports the following (architecture, ABI) combinations, with dynamic linker names as indicated. There may well be other cases of configure triplets and --with-fp / --without-fp options accepted by configure, but they are unlikely actually to work.

The expectation is that binaries and shared libraries from different ABIs on this list cannot be loaded in the same process, and if possible the dynamic linker should check compatibility and prevent attempts to load them, but that binaries and shared libraries from the same ABI will interoperate as long as the processor supports the instructions required by all relevant code. (It is possible that cases of mixed ABIs may appear to work sometimes, for example if functions with floating-point arguments and return values are not used and that is the only difference in the ABIs, but this is not considered a supported use of glibc.)

The entries for sparc are awaiting architecture maintainer confirmation that soft-float is not in use for that architecture. Architecture maintainers should check their entries, correct them as needed them remove references to their architectures in this paragraph.

Hurd

x86

Linux kernel

aarch64

(The ILP32 port is not yet in glibc.)

alpha

arc

(ARC function-calling ABI is the same for both hard and soft-float)

arm

(The ARM soft-float ABI can be used with both hard and soft-float code. ARM supports two variants of big-endian operation, (on newer processors) BE8 and (on older processors) BE32, which are the same at .o level but incompatible for linked executables and shared libraries.)

C-SKY

hppa

ia64

loongarch

m68k

(The ColdFire function-calling ABI is the same for both hard and soft-float, but the glibc ABI, e.g. size of jmp_buf, is different.)

microblaze

mips

nios2

or1k

(On OpenRISC "hard-float" and "soft-float" have the same ABI, there is not a separate floating point register set, general purpose registers are used for both integers and floats and calling conventions do not change.)

powerpc

(The GCC distinction for 64-bit is actually ELFv1/ELFv2, but the BE ELFv2 and LE ELFv1 combinations aren't supported.)

RISC-V

("hard-float" and "soft-float" here refer to the ABI, which is distinct from the target ISA. Specifically, the soft-float ABI can target ISAs with hardware floating point instructions.)

s390

sh

sparc

x86 / x86_64

None: ABIList (last edited 2024-05-04 21:22:26 by StaffordHorne)