Bug 32036 - RISC-V zcmp: unrecognized opcode `cm.mva01s s0,s1'
Summary: RISC-V zcmp: unrecognized opcode `cm.mva01s s0,s1'
Status: RESOLVED FIXED
Alias: None
Product: binutils
Classification: Unclassified
Component: gas (show other bugs)
Version: 2.44 (HEAD)
: P2 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2024-07-29 22:59 UTC by Patrick O'Neill
Modified: 2024-08-27 02:28 UTC (History)
2 users (show)

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Host:
Target: riscv*-*-*
Build:
Last reconfirmed:

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Description Patrick O'Neill 2024-07-29 22:59:18 UTC 
Binutils output:
/tmp/cczUKUoq.s: Assembler messages:
/tmp/cczUKUoq.s:33: Error: unrecognized opcode `cm.mva01s s0,s1'
Compiler returned: 1

GCC 15 emits cm.mva01s s0,s1 which appears to match the asm in the spec:
cm.mva01s r1s', r2s'

Spec (v1.0.4-3): https://github.com/riscvarchive/riscv-code-size-reduction/releases

Godbolt: https://godbolt.org/z/W5G48qc3h
Comment 1 Nelson Chu 2024-07-30 02:22:10 UTC 
The xventana cond extension are rv64 only since this patch, https://github.com/bminor/binutils-gdb/commit/fe0f44a0caf59db09ad4bc16a46926aba96ce60d
Comment 2 Patrick O'Neill 2024-08-02 21:05:06 UTC 
It looks like the patch is here with a LGTM: https://sourceware.org/pipermail/binutils/2024-February/132263.html

Patch 1/2 wasn't approved for v6 and v7 dropped 2/2: https://sourceware.org/pipermail/binutils/2024-April/133473.html

Patch 2/2 doesn't apply cleanly anymore but I didn't investigate further.
Comment 3 Sourceware Commits 2024-08-27 02:26:37 UTC 
The master branch has been updated by Nelson Chu <nelsonc1225@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ca2590d7804b4ea563eec6f1127ed17a00c30315

commit ca2590d7804b4ea563eec6f1127ed17a00c30315
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Tue Aug 20 10:10:21 2024 +0800

    RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.
    
    This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'.
    All disassemble instructions use the sreg format.
    
    Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
    Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
    Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
    Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
    Co-Authored by: Simon Cook <simon.cook@embecosm.com>
    Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
    Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
    
    gas/ChangeLog:
            PR 32036
            * NEWS: Updated.
            * config/tc-riscv.c (validate_riscv_insn): New operators.
            (riscv_ip): Ditto.
            * testsuite/gas/riscv/zcmp-mv.d: New test.
            * testsuite/gas/riscv/zcmp-mv.s: New test.
    
    include/ChangeLog:
            PR 32036
            * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode.
            (MASK_CM_MVA01S): New mask.
            (MATCH_CM_MVSA01): New opcode.
            (MASK_CM_MVSA01): New mask.
            (DECLARE_INSN): New declarations.
            * opcode/riscv.h (OP_MASK_SREG1): New mask.
            (OP_SH_SREG1): New operand code.
            (OP_MASK_SREG2): New mask.
            (OP_SH_SREG2): New operand code.
            (X_A0): New reg number.
            (X_A1): Ditto.
            (X_S7): Ditto.
            (RISCV_SREG_0_7): New macro function.
    
    opcodes/ChangeLog:
            PR 32036
            * riscv-dis.c (riscv_zcmp_get_sregno): New function.
            (print_insn_args): New operators.
            * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
Comment 4 Nelson Chu 2024-08-27 02:28:48 UTC 
Marked as resolved and fixed.