Bug 30494 - [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to terminate
Summary: [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to...
Status: RESOLVED INVALID
Alias: None
Product: gdb
Classification: Unclassified
Component: sim (show other bugs)
Version: 12.1
: P2 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL: https://github.com/riscv-collab/riscv...
Keywords:
Depends on:
Blocks:
 
Reported: 2023-05-27 14:52 UTC by Tommy Murphy
Modified: 2023-05-27 16:48 UTC (History)
3 users (show)

See Also:
Host:
Target: riscv
Build:
Last reconfirmed:


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Description Tommy Murphy 2023-05-27 14:52:13 UTC
Originally discussed here:

https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1200

As far as I can see (and as outlined here: https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1200#issuecomment-1451965016) the ori x0, xn, imm instruction is getting decoded as the wrong class (INSN_CLASS_ZBC_OR_ZBKC instead of INSN_CLASS_I) and the simulator terminates with an UNHANDLED_EXTENSION message.

If any additional info is needed please let me know - thanks.
Comment 1 Tom Tromey 2023-05-27 16:32:57 UTC
I suspect this is more of a libopcodes bug than a sim bug.
Not sure which component is right for libopcodes though.
I'd say the binutils product but I don't see a libopcodes component.
Comment 2 Tommy Murphy 2023-05-27 16:44:18 UTC
Hi Tom - thanks for the reply. Looks like libopcodes bugs should be logged against binutils alright:

https://sourceware.org/bugzilla/buglist.cgi?bug_status=UNCONFIRMED&bug_status=NEW&bug_status=ASSIGNED&bug_status=SUSPENDED&bug_status=WAITING&bug_status=REOPENED&list_id=75317&product=binutils&query_format=advanced&short_desc=libopcodes&short_desc_type=allwordssubstr

I'll log it there instead and close this one. 

Thanks again.
Regards
Tommy
Comment 3 Tommy Murphy 2023-05-27 16:48:36 UTC
Logged against binutils/libopcodes here:

https://sourceware.org/bugzilla/show_bug.cgi?id=30495