Bug 27023 - [ARM]: ldrd/strd without second transfer register
Summary: [ARM]: ldrd/strd without second transfer register
Status: UNCONFIRMED
Alias: None
Product: binutils
Classification: Unclassified
Component: binutils (show other bugs)
Version: 2.35
: P2 minor
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2020-12-06 04:03 UTC by husseydevin
Modified: 2022-06-22 06:29 UTC (History)
1 user (show)

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Target: arm-none-eabi
Build:
Last reconfirmed:

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Description husseydevin 2020-12-06 04:03:59 UTC 
ARM objdump annotates ldrd/strd with only one transfer register.

So, for example, 

     ldrd    r0, r1, [r2]
     strd    r0, r1, [r2]

Will dump as

     ldrd    r0, [r2]
     strd    r0, [r2]

Both registers should be annotated:

 - It matches the ARM documentation
 - It matches the behavior of llvm-objdump and radare2
 - It will be impossible to mix up with ldrb/strb, as they no longer line up visually

Additionally, gas *accepts* this one operand syntax. Is this intentional?