The following assembly will be wrongly rejected if mve is enabled: .syntax unified .text itt lt vsublt.f32 s0, s1, s2 vaddlt.f32 s0, s1, s2 This is because I forgot to allow for single precision register parsing for vsubl/vaddl which is what gets matched when MVE is enabled as 't' is stripped as a potential true lane predication suffix.
Fixed in master 2.34 and 2.33