Created attachment 12148 [details] Extract from ARM A64 Instruction Set Architecture Manual. I tried to debug my application with Aarch64 simulator of GDB, and I got a crash. After some debugging, I discovered that the implementation of BLR opcode is bugged because it does not support XLR register as parameter. Actually, there are no restrictions to the register to be used, but the current code is wrong because aarch64_save_LR() overwrites the address inside XLR before it can be used with aarch64_set_next_PC(). I also attached a screenshot taken from the ARM A64 Instruction Set Architecture manual which shows clearly that target address is acquired before writing X[30]. Attached patch fixes this bug. While compiling the Aarch64 simulator, I also got two little problems: - in function ldrsw_abs() which is void but returning a value. - function dexBranchImmediate() is also void, but used for returning a value. Since they were extremely simple, I also included them into the attached patch. Sincerely.
Created attachment 12149 [details] Proposed patch
The aarch64 gdb sim port is incomplete and not actively maintained. If you need a simulator, you are much better off using qemu which is actively maintained, unless perhaps you want to volunteer to help finish the aarch64 sim port. If you do want to work on this, then you need an FSF copyright assignment. I don't see an obvious one for you on file at the FSF, but maybe your employer has one? The patch does look OK to me. Maybe it is small enough and obvious enough to accept without an assignment?
> Maybe it is small enough and obvious enough to accept without an assignment? I hope that it could be possible. As you said, it is true that QEMU is more advanced in terms of speed and compatibility: implementation of some opcodes is also missing inside the Aarch64 simulator of GDB, but actually it was more than enough for my hobbyist development and it covered all my needs without using an host OS. Thank you very much for your time. Sincerely.
Hi Carlo, Could you please send your patch to the gdb-patches mailing list? This is where the patch review/handling is done. More details here: https://sourceware.org/gdb/wiki/ContributionChecklist Thanks!
The master branch has been updated by Andrew Burgess <aburgess@sourceware.org>: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 commit 69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 Author: Carlo Bramini <carlo_bramini@users.sourceforge.net> Date: Thu Feb 6 22:50:26 2020 +0000 sim/aarch64: Fix register ordering bug in blr (PR sim/25318) A comment in the implementation of blr says: /* The pseudo code in the spec says we update LR before fetching. the value from the rn. */ With 'rn' being the register holding the destination address. This may have been true at one point, but the ISA manual now clearly shows the destination register being read before the link register is written. This commit updates the implementation of blr to match. sim/aarch64/ChangeLog: PR sim/25318 * simulator.c (blr): Read destination register before calling aarch64_save_LR. Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064
(In reply to cvs-commit@gcc.gnu.org from comment #5) > The master branch has been updated by Andrew Burgess > <aburgess@sourceware.org>: > > https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git; > h=69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 The commit has fixed the issue. So, this bug could be marked as resolved if you want. Thank you very much for your support. Sincerely.
(In reply to Carlo Bramini from comment #6) > (In reply to cvs-commit@gcc.gnu.org from comment #5) > > The master branch has been updated by Andrew Burgess > > <aburgess@sourceware.org>: > > > > https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git; > > h=69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 > > The commit has fixed the issue. > So, this bug could be marked as resolved if you want. > Thank you very much for your support. > > Sincerely. Done, thanks.