Bug 23193 - aarch64: orr should not be converted to alias mov when non-zero shift
Summary: aarch64: orr should not be converted to alias mov when non-zero shift
Status: RESOLVED FIXED
Alias: None
Product: binutils
Classification: Unclassified
Component: binutils (show other bugs)
Version: 2.30
: P2 normal
Target Milestone: 2.32
Assignee: Not yet assigned to anyone
URL:
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Depends on:
Blocks:
 
Reported: 2018-05-17 06:15 UTC by Raimar Falke
Modified: 2018-12-03 18:08 UTC (History)
1 user (show)

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Description Raimar Falke 2018-05-17 06:15:52 UTC
$ hexdump bin2
0000000 ee f3 9e aa                                    
0000004
$ objdump -D -b binary -maarch64 -Mno-aliases bin2

bin2:     file format binary


Disassembly of section .data:

0000000000000000 <.data>:
   0:	aa9ef3ee 	orr	x14, xzr, x30, asr #60
$ objdump -D -b binary -maarch64 bin2

bin2:     file format binary


Disassembly of section .data:

0000000000000000 <.data>:
   0:	aa9ef3ee 	mov	x14, x30, asr #60
$

The condition for the alias is 
  shift == '00' && imm6 == '000000' && Rn == '11111'
here imm6 (the shift amount) is clearly not all zeros 
and therefore the output of no-aliases and aliases should be the 
same (the orr variant).
Comment 1 cvs-commit@gcc.gnu.org 2018-12-03 17:35:41 UTC
The master branch has been updated by Richard Earnshaw <rearnsha@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=57b64c4103ffeadd524eb80b4a7d61be8c8ec871

commit 57b64c4103ffeadd524eb80b4a7d61be8c8ec871
Author: Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
Date:   Mon Dec 3 17:31:44 2018 +0000

    [aarch64] - Only use MOV for disassembly when shifter op is LSL #0
    
    ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
    states that MOV (register) is an alias of the ORR (shifted register)
    iff shift == '00' && imm6 == '000000' && Rn == '11111'.  However, mov
    is currently preferred for a broader range of orr instructions, which
    is incorrect.
    
    2018-12-03  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
    
    opcodes:
    	PR 23193
            PR 19721
            * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
    	encoding as MOV if the shift operation is a left shift of zero.
    
    gas:
    	PR 23193
    	PR 19721
    	* testsuite/gas/aarch64/pr19721.s: Add new test cases.
    	* testsuite/gas/aarch64/pr19721.d: Correct existing test
    	cases and add new ones.
Comment 2 Tamar Christina 2018-12-03 18:08:57 UTC
Fixed in mainline.