This enhancement has the same text as: https://sourceware.org/bugzilla/show_bug.cgi?id=22969 but applies to ld.bfd and not ld.gold. In a recent change to LLVM (https://reviews.llvm.org/D44355) an attempt was made to fold the add and the ldr in the sequence: mrs x1, TPIDR_EL0 add x2, x1, :tprel_hi12:local_exec_var add x3, x2, :tprel_lo12_nc:local_exec_var ldr w0, [x3] to: mrs x1, TPIDR_EL0 add x2, x1, :tprel_hi12:local_exec_var ldr w0, [x2, :tprel_lo12_nc:local_exec_var] Unfortunately for this to work support is needed for the R_AARCH_TLSLE_LDST8_TPREL_LO12 relocation that ldr w0, [x2, :tprel_lo12_nc:local_exec_var] uses. It looks like only R_AARCH64_TLSLE_ADD_TPREL_LO12 is supported in binutils trunk (gold and bfd right now). It would be nice to add support for that relocation to enable the relaxation.
Created attachment 10907 [details] Proposed patch Hi Peter, Please could you try out this patch and let me know if it works for you ? I am especially concerned that I might have missed something when evaluating the TLSLE_LDST8_LO12_NC reloc in the linker, so if you can, please check that linked binaries do actually work as expected... :-) Cheers Nick
Hello Nick, Thanks for the patch. I'm travelling at the moment; I will try this out when I get back to the office on Monday. Peter
Hello Nick, I've been able to try out the patch. It looks like it is doing what I'd expect for the R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC relocation. When I went back to the original LLVM patch, I tried the example and got a missing relocation error. It looks like my PR was incomplete; I missed out: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC These correspond to the halfword, 32-bit and 64-bit word load instructions (the LDST8 is the byte load instruction). My apologies for missing these out, would it be possible to consider these as well as they could be generated by a compiler with the same llvm patch? An example to that can be assembled with clang --target=aarch64-linux-gnu generates these relocations. .text .globl _start .type _start, %function _start: mrs x8, TPIDR_EL0 add x8, x8, :tprel_hi12:var0 ldr x0, [x8, :tprel_lo12_nc:var0] add x8, x8, :tprel_hi12:var1 ldr w0, [x8, :tprel_lo12_nc:var1] add x8, x8, :tprel_hi12:var2 ldrh w0, [x8, :tprel_lo12_nc:var2] add x8, x8, :tprel_hi12:var3 ldrb w0, [x8, :tprel_lo12_nc:var3] .globl var0 .globl var1 .globl var2 .globl var3 .type var0,@object .type var1,@object .type var2,@object .type var3,@object .section .tbss,"awT",@nobits .p2align 2 var0: .quad 0 .size var1, 8 var1: .word 0 .size var1, 4 var2: .hword 0 .size var2, 2 var3: .byte 0 .size var3, 1
Hi Peter, > My apologies for missing these out, would it be possible to consider these > as well as they could be generated by a compiler with the same llvm patch? Yes, but ... I am hoping that Renlin Li will take over fixing this PR, as he has expressed an interest in adding support for all of these relocations. I will keep an eye on this PR however, and if necessary, have another go myself. Cheers Nick
The support of following relocations has been checked into binutils now. BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC. Both ip64 and ilp32 variants are now supported in gas and bfd linker. https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=84f1b9fb081372a726fd70dfd8258a707833caef https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=e04ef02299ad4aae08da857e8535d98e8643a274 This issue should be resolved now.