[hjl@gnu-6 testsuite]$ cat /tmp/x.s .text movd 128(%rax), %xmm1 movd %rax, %xmm1 movd %xmm1, 128(%rax) movd %xmm1, %rax vmovd 128(%rax), %xmm1 vmovd %rax, %xmm1 vmovd %xmm1, 128(%rax) vmovd %xmm1, %rax {evex} vmovd 128(%rax), %xmm1 {evex} vmovd %xmm1, 128(%rax) .intel_syntax noprefix movd xmm1, qword ptr [rax + 128] movd xmm1, rax movd qword ptr [rax + 128], xmm1 movd rax, xmm1 vmovd xmm1, qword ptr [rax + 128] vmovd xmm1, rax vmovd qword ptr [rax + 128], xmm1 vmovd rax, xmm1 {evex} vmovd xmm1, qword ptr [rax + 128] {evex} vmovd qword ptr [rax + 128], xmm1 [hjl@gnu-6 testsuite]$ gcc -c /tmp/x.s [hjl@gnu-6 testsuite]$ objdump -dw -Mintel x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 66 0f 6e 88 80 00 00 00 movd xmm1,DWORD PTR [rax+0x80] 8: 66 48 0f 6e c8 movq xmm1,rax d: 66 0f 7e 88 80 00 00 00 movd DWORD PTR [rax+0x80],xmm1 15: 66 48 0f 7e c8 movq rax,xmm1 1a: c5 f9 6e 88 80 00 00 00 vmovd xmm1,DWORD PTR [rax+0x80] 22: c4 e1 f9 6e c8 vmovq xmm1,rax 27: c5 f9 7e 88 80 00 00 00 vmovd DWORD PTR [rax+0x80],xmm1 2f: c4 e1 f9 7e c8 vmovq rax,xmm1 34: 62 f1 7d 08 6e 48 20 vmovd xmm1,DWORD PTR [rax+0x80] 3b: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR [rax+0x80],xmm1 42: 66 48 0f 6e 88 80 00 00 00 movq xmm1,QWORD PTR [rax+0x80] 4b: 66 48 0f 6e c8 movq xmm1,rax 50: 66 48 0f 7e 88 80 00 00 00 movq QWORD PTR [rax+0x80],xmm1 59: 66 48 0f 7e c8 movq rax,xmm1 5e: c5 f9 6e 88 80 00 00 00 vmovd xmm1,DWORD PTR [rax+0x80] This should be QWORD. 66: c4 e1 f9 6e c8 vmovq xmm1,rax 6b: c5 f9 7e 88 80 00 00 00 vmovd DWORD PTR [rax+0x80],xmm1 This should be QWORD. 73: c4 e1 f9 7e c8 vmovq rax,xmm1 78: 62 f1 7d 08 6e 48 20 vmovd xmm1,DWORD PTR [rax+0x80] This should be QWORD. 7f: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR [rax+0x80],xmm1 This should be QWORD. [hjl@gnu-6 testsuite]$
The master branch has been updated by H.J. Lu <hjl@sourceware.org>: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=704a705d7aaab8041df76e2981e2a1efc014aad0 commit 704a705d7aaab8041df76e2981e2a1efc014aad0 Author: H.J. Lu <hjl.tools@gmail.com> Date: Mon Jan 8 04:36:59 2018 -0800 x86: Properly encode vmovd with 64-bit memeory For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
Fixed for 2.30.