Bug 18692 - AArch64: ld --emit-relocs corrupts section relative relocations
Summary: AArch64: ld --emit-relocs corrupts section relative relocations
Status: RESOLVED INVALID
Alias: None
Product: binutils
Classification: Unclassified
Component: ld (show other bugs)
Version: 2.24
: P2 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2015-07-19 15:39 UTC by Ard Biesheuvel
Modified: 2015-07-23 10:09 UTC (History)
1 user (show)

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Description Ard Biesheuvel 2015-07-19 15:39:49 UTC
When merging ELF sections together, section relative relocations emitted using --emit-relocs do not have their addends recalculated, leading to corrupt relocation data.

For instance, after assembling the following code:

	.text
	.skip	0x20
	.quad	sym1
	.section ".rodata"
sym1:
	.skip	0x38
	.word	0x0

using "aarch64-linux-gnu-as -o /tmp/rela.o /tmp/rela.s", the resulting rela.text section contains:

Relocation section '.rela.text' at offset 0x3f0 contains 1 entries:
  Offset          Info           Type           Sym. Value    Sym. Name + Addend
000000000020  000600000101 R_AARCH64_ABS64   0000000000000000 .rodata + 38


However, after linking it using the following script:

SECTIONS {
	.text : { *(.text .rodata) }
}

using "aarch64-linux-gnu-ld -e 0x0 -o /tmp/rela /tmp/rela.o --emit-relocs -T /tmp/rela.lds", the resulting rela.text section contains the following relocation:

Relocation section '.rela.text' at offset 0x10298 contains 1 entries:
  Offset          Info           Type           Sym. Value    Sym. Name + Addend
000000000020  000100000101 R_AARCH64_ABS64   0000000000000000 .text + 38

Here, the RELA addend is unchanged, even though the original .rodata is placed 0x28 bytes into .text.
Comment 1 Jiong Wang 2015-07-23 09:40:45 UTC
please try trunk binutils, looks like fixed by the following commit already.

commit 2e0488d33f8abbbc5bec214e1723d07048d7afcc
Author: Jiong Wang <jiong.wang@arm.com>
Date:   Tue Jul 8 09:29:06 2014 +0100

    Enable elf_backend_rela_normal for AArch64
Comment 2 Ard Biesheuvel 2015-07-23 10:06:15 UTC
Yes, you are right. Sorry for the noise.
Comment 3 Jiong Wang 2015-07-23 10:09:12 UTC
mark as invalid.