The ARM architecture has certain instruction encodings specified as permanently undefined (guaranteed to generate an Undefined Instruction exception), and these have a defined UDF mnemonic to generate them, but gas does not know that mnemonic. ("Issue C.a of this manual first defines an assembler mnemonic for these encodings.", according to DDI0406C.b.)
CVSROOT: /cvs/src Module name: src Changes by: nickc@sourceware.org 2013-09-04 07:59:33 Modified files: gas : ChangeLog gas/config : tc-arm.c gas/testsuite : ChangeLog opcodes : ChangeLog arm-dis.c Added files: gas/testsuite/gas/arm: udf-bad.d udf-bad.l udf-bad.s udf.d udf.l udf.s Log message: PR gas/15914 * config/tc-arm.c (T16_32_TAB): Add _udf. (do_t_udf): New function. (insns): Add "udf". * gas/arm/udf-bad.s: New file. * gas/arm/udf-bad.d: New file. * gas/arm/udf-bad.l: New file. * gas/arm/udf.s: New file. * gas/arm/udf.d: New file. * gas/arm/udf.l: New file. * arm-dis.c (arm_opcodes): Add udf. (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. (thumb32_opcodes): Add udf.w. (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says. Patches: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/ChangeLog.diff?cvsroot=src&r1=1.5101&r2=1.5102 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-arm.c.diff?cvsroot=src&r1=1.576&r2=1.577 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.2292&r2=1.2293 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/udf-bad.d.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/udf-bad.l.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/udf-bad.s.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/udf.d.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/udf.l.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/udf.s.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.2020&r2=1.2021 http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.171&r2=1.172
Patch applied