Bug 10288 - "objdump -D --target=binary -m arm7tdmi" shows non-ARM7TDMI instructions
Summary: "objdump -D --target=binary -m arm7tdmi" shows non-ARM7TDMI instructions
Status: WAITING
Alias: None
Product: binutils
Classification: Unclassified
Component: binutils (show other bugs)
Version: 2.19
: P2 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2009-06-16 18:32 IST by Chris Seberino
Modified: 2016-05-16 17:11 IST (History)
3 users (show)

See Also:
Host:
Target:
Build:
Last reconfirmed:


Attachments
Use -m to restrict ARM disassembly (6.78 KB, patch)
2009-06-17 12:22 IST, Nick Clifton
Details | Diff
Fix coprocessor opcode discrimination (2.35 KB, patch)
2009-06-19 14:51 IST, Nick Clifton
Details | Diff
Combination patch for pr 10297 and 10288 (2.35 KB, patch)
2009-06-22 11:45 IST, Nick Clifton
Details | Diff
Fix a few more disasssembly mistakes (22.78 KB, patch)
2009-06-24 16:40 IST, Nick Clifton
Details | Diff
Updated version of previous patch (22.77 KB, patch)
2009-06-25 07:16 IST, Nick Clifton
Details | Diff
More disassembly consistency improvements (1.02 KB, patch)
2009-06-30 11:58 IST, Nick Clifton
Details | Diff
Catch unexpected STRB scaled addressing modes (353 bytes, patch)
2009-07-07 14:44 IST, Nick Clifton
Details | Diff
Addressing mode fixes (1.33 KB, patch)
2009-07-14 14:17 IST, Nick Clifton
Details | Diff

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Description Chris Seberino 2009-06-16 18:32:39 IST
objdump for ARM7TDMI binaries shows instructions for newer ARM architectures.

It doesn't return "undefined" like it should for these instructions.
Comment 1 Nick Clifton 2009-06-17 12:22:48 IST
Created attachment 4003 [details]
Use -m to restrict ARM disassembly
Comment 2 Nick Clifton 2009-06-17 12:24:44 IST
Hi Chris,

  Thanks for reporting this problem.  Please could you try out the uploaded
patch and let me know how you get on with it.  (Note - you will need to remove
the earlier version of this patch sent to you via the mailing list).

  This version should handle the coprocessor instructions as well as the base
architecture instructions and it now uses the ARM_FEATURE macros to chose the
core architecture and coprocessor extensions.

Cheers
  Nick
Comment 3 Chris Seberino 2009-06-18 03:34:14 IST
You were certainly correct to remove certain coprocessor instructions like ldc2
that only belong on later architectures.

I'm not sure we're allowed to remove *all* coprocessor instructions.

Even though many (most?) fielded ARM7TDMIs don't utilize coprocessors or virtual
floating point instructions, I think they are still recognized by ARM7TDMI.

What was your rationale for remove *all* coprocessor instructions?
Comment 4 cvs-commit@gcc.gnu.org 2009-06-18 10:31:36 IST
Subject: Bug 10288

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2009-06-18 10:31:21

Modified files:
	include        : ChangeLog dis-asm.h 
	gas/testsuite  : ChangeLog 
	gas/testsuite/gas/arm: align.s copro.d 
	opcodes        : ChangeLog arm-dis.c 
	binutils       : ChangeLog objdump.c 
	binutils/doc   : binutils.texi 

Log message:
	PR 10288
	* arm-dis.c (print_insn_coprocessor): Check that a user specified
	ARM architecture supports the matched instruction.
	(print_insn_arm): Likewise.
	(select_arm_features): New function.  Fills in the fields of an
	arm_feature_set structure based on a given arm machine number.
	(print_insn): Initialise an arm_feature_set structure.
	
	* objdump.c (disassemble_bytes): Set the
	USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure
	if the user has invoked the -m switch.
	* doc/binutils.texi: Document the additional behaviour of
	objdump's -m switch for ARM targets.
	
	* dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
	field of struct disassemble_info.
	
	* gas/arm/align.s: Add labels so that COFF based targets can
	correctly locate THUMB code.
	* gas/arm/copro.d: Do not pass --architecture switch to objdump.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/ChangeLog.diff?cvsroot=src&r1=1.450&r2=1.451
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/dis-asm.h.diff?cvsroot=src&r1=1.73&r2=1.74
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1492&r2=1.1493
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/align.s.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/copro.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1402&r2=1.1403
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.97&r2=1.98
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/binutils/ChangeLog.diff?cvsroot=src&r1=1.1485&r2=1.1486
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/binutils/objdump.c.diff?cvsroot=src&r1=1.158&r2=1.159
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/binutils/doc/binutils.texi.diff?cvsroot=src&r1=1.147&r2=1.148

Comment 5 Nick Clifton 2009-06-18 10:38:34 IST
Hi Chris,

  Right, first of all, I have checked in the patch along with the changelog
entries below.

  Secondly you asked: "What was your rationale for remove *all* coprocessor
instructions?"  The answer is that I did not.  I just restricted the coprocessor
instruction display to those that are guaranteed to be supported by the given
architecture, as determined by the macros in the include/opcode/arm.h file.  If
the user wants to see all the coprocessor instructions they can invoke the
disassembler with the "-marm" switch.

Cheers
  Nick

include/ChangeLog
2009-06-18  Nick Clifton  <nickc@redhat.com>

	* dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
	field of struct disassemble_info.

opcodes/ChangeLog
2009-06-18  Nick Clifton  <nickc@redhat.com>

	PR 10288
	* arm-dis.c (print_insn_coprocessor): Check that a user specified
	ARM architecture supports the matched instruction.
	(print_insn_arm): Likewise.
	(select_arm_features): New function.  Fills in the fields of an
	arm_feature_set structure based on a given arm machine number.
	(print_insn): Initialise an arm_feature_set structure.

binutils/ChangeLog
2009-06-18  Nick Clifton  <nickc@redhat.com>

	PR 10288
	* objdump.c (disassemble_bytes): Set the
	USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure
	if the user has invoked the -m switch.
	* doc/binutils.texi: Document the additional behaviour of
	objdump's -m switch for ARM targets.

gas/testsuite/ChangeLog
2009-06-18  Nick Clifton  <nickc@redhat.com>

	PR 10288
	* gas/arm/align.s: Add labels so that COFF based targets can
	correctly locate THUMB code.
	* gas/arm/copro.d: Do not pass --architecture switch to objdump.


Comment 6 Chris Seberino 2009-06-18 18:33:20 IST
I think your patch may have done more than you think.  It not only removed
coprocessor instructions that are not supported by ARM7TDMI, but also removed
coprocessor instructions that *are* supported by ARM7TDMI.  For example, I don't
see ldc anymore which *is* supported by ARM7TDMI.  Not it is reported as undefined.

The problem with your suggestion of using the "-marm" switch is that is would
return the problem that existed before...namely, showing coprocessors
instructions for newer architectures that shouldn't be there like ldc2.
Comment 7 Nick Clifton 2009-06-19 14:51:02 IST
Created attachment 4009 [details]
Fix coprocessor opcode discrimination
Comment 8 Nick Clifton 2009-06-19 14:51:55 IST
Hi Chris,

  I take your point.  Please try out the uploaded additional patch which should
fix this.

Cheers
  Nick
Comment 9 Chris Seberino 2009-06-19 17:50:26 IST
I can't apply patch from bug #10288 and bug #10297 at same time.
They crash into each other when you try to apply both of them.

Can you make a patch that includes both fixes?

chris
Comment 10 Nick Clifton 2009-06-22 11:45:28 IST
Created attachment 4011 [details]
Combination patch for pr 10297 and 10288
Comment 11 Nick Clifton 2009-06-22 11:45:58 IST
Hi Chris,

  Please try out the newly uploaded, combined patch.

Cheers
  Nick
Comment 12 Chris Seberino 2009-06-22 19:43:50 IST
The undefined fix is very nice.  I did find some issues and have appended a
Python script to reproduce...


#==========The Python script============================================

import struct
raw_binary = open("raw_binary", "w")
raw_binary.write(struct.pack("L", 0x4c585ee5))
raw_binary.write(struct.pack("L", 0x01a23597))
raw_binary.write(struct.pack("L", 0x3d9da24e))

#==========The Python script output=====================================

% objdump -D --target=binary -m arm7tdmi raw_binary

raw_binary:     file format binary


Disassembly of section .data:

00000000 <.data>:
   0:	4c585ee5 	mrrcmi	14, 14, r5, r8, cr5
   4:	01a23597 	strbeq	r3, [r2, r7]!
   8:	3d9da24e 	lfmcc	f2, 1, [sp, #312]

#==================Comments======================================

1. mrrcmi is an extended DSP instruction that doesn't belong on ARM7TDMI right?

2. According to my ARM ref manual, strb needs to have bits 4-11 zeroed out which
01a23597 doesn't.  Should this be undefined instead?

3. I can't find lfm in my ARM ref manual.  Googling reveal it to be a floating
point multiple load instruction.  This may be right but I'm not sure since it
isn't documented in ARM book I have.

cs
Comment 13 Chris Seberino 2009-06-22 21:53:08 IST
I was thinking a little more about the lfm instruction.  It seems there are
standard coprocessor instruction names on ARM: cdp, ldc, stc, mcr and mrc.

And, because ARM defines optional standard coprocessor setups for common
hardware extensions like floating point, ARM has defined additional *ALIASES*
for aforementioned coprocessor instructions like lfm, fstms, fstmd, fstd, fstd, etc.

I would personally prefer that only the standard coprocessor instruction names
be used (cdp, ldc, stc, mcr and mrc) and the other aliases like floating point
aliases be avoided since we can't guarantee existence of that.

cs
Comment 14 Nick Clifton 2009-06-24 16:40:31 IST
Created attachment 4019 [details]
Fix a few more disasssembly mistakes
Comment 15 Nick Clifton 2009-06-24 16:45:28 IST
Hi Chris,

> 1. mrrcmi is an extended DSP instruction that doesn't belong on ARM7TDMI right?

Right.  This was a typo in the arm-dis.c file.

> 2. According to my ARM ref manual, strb needs to have bits 4-11 zeroed out
which 01a23597 doesn't.  Should this be undefined instead?

Yes it should.  The disassembly patterns were being a bit too generous.


> 3. I can't find lfm in my ARM ref manual.

Neither can I.  As found out it appears to be a variant of the LDC instruction,
but it is not a true alias for it - there is actually a difference syntax to the
instruction and a different bit encoding.  (It uses bits 11 and 22 to encode a
'count' value).

The uploaded patch fixes 1 and 2.  I have to assume that the encoding and
decoding for LFM, and presumably SFM, are correct.  I also assume that they are
defined in one of the proprietary versions of the ARM Architecture Reference
Manual that ARM only gives out to its approved, registered customers.

Cheers
  Nick

PS.  The uploaded patch includes the previous patches for this issue and the
patches for issue 10297.
Comment 16 Chris Seberino 2009-06-24 20:14:22 IST
mrrc is gone with is good.  strb appears to have gotten worse! I think the new
patch introduced new bugs into strb.  See below.  Also, some hex equivalents
appear to be botched.  See below for that too....

New objdump shows following instructions to be strb but I think they should be
all undefined....

46647659 	strbmi	r7, [r4], #-105
77c1cdb4 	strbvc	ip, [r1, #212]
e640361f 	strb	r3, [r0], #-111

Notice following have incorrect or missing hex equivalents...

4c585ee5 	ldclmi	14, cr5, [r8], {229}	; 0xfffffc6c
d446399e 	strble	r3, [r6], #-158
11d87ed1 	ldrsbne	r7, [r8, #225]
44afa697 	strtmi	sl, [pc], #1687	; 0xb4
d4bf78b4 	ldrtle	r7, [pc], #2228	; 0xf4
bc041350 	stclt	3, cr1, [r4], {80}	; 0xfffffec0

chris
Comment 17 Chris Seberino 2009-06-24 22:32:03 IST
About lfm and sfm.....these are alternative aliases for floating point
coprocessor instructions along with many others in the ARM docs I've seen.

We can't guarantee that every ARM7TDMI will have a floating point coprocessor so
these aliases will not always apply.

Wouldn't it therefore be safer and make more sense to have objdump just display
the standard coprocessor instruction names?... (i.e. ldc, stc, cdp ?)

Comment 18 Nick Clifton 2009-06-25 07:16:49 IST
Created attachment 4020 [details]
Updated version of previous patch
Comment 19 Nick Clifton 2009-06-25 07:17:35 IST
Hi Chris,

  Oops, please ignore the previous patch.  I had not checked it thoroughly
enough.  I have uploaded a revised version which should be better.

Cheers
  Nick
Comment 20 Chris Seberino 2009-06-25 18:26:11 IST
** Incorrect or missing hex equivalents...
(If this is hard to fix and you want to just remove all hex equivalents that
would be fine by me.)

4c585ee5 	ldclmi	14, cr5, [r8], {229}	; 0xfffffc6c
11d87ed1 	ldrsbne	r7, [r8, #225]
44afa697 	strtmi	sl, [pc], #1687	; 0xb4
d4bf78b4 	ldrtle	r7, [pc], #2228	; 0xf4
bc041350 	stclt	3, cr1, [r4], {80}	; 0xfffffec0

** Notice the very last argument for these 3 strb's are registers.  It doesn't
appear in my ARM ref book for addressing mode 2.  In other words, to the right
of asr, lsl, lsr and ror should only be immediate values.

46647659 	strbmi	r7, [r4], -r9, asr r6
e640361f 	strb	r3, [r0], -pc, lsl r6
77c1cdb4 	strbvc	ip, [r1, r4, lsr sp]

** What did you think of my reasons for replacing floating point aliases like
lfm with the always correct standard names like ldc?  This would apply for
example to this one...

3d9da24e 	lfmcc	f2, 1, [sp, #312]	; 0x138
Comment 21 cvs-commit@gcc.gnu.org 2009-06-29 08:08:32 IST
Subject: Bug 10288

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2009-06-29 08:08:15

Modified files:
	opcodes        : ChangeLog arm-dis.c 
	gas/testsuite  : ChangeLog 
	gas/testsuite/gas/arm: arch6zk.d arch7.d arm-it-auto-2.d 
	                       arm-it-auto.d copro.d float.d fpa-mem.d 
	                       group-reloc-ldc.d group-reloc-ldr.d 
	                       iwmmxt.d maverick.d neon-omit.d svc.d 
	                       thumb-eabi.d thumb.d thumb1_unified.d 
	                       thumb2_add.d thumb2_relax.d thumb32.d 
	                       vfp-neon-syntax.d vfp-neon-syntax_t2.d 
	                       vfp1xD.d vfp1xD_t2.d vfpv3-const-conv.d 
	                       xscale.d 
	ld/testsuite   : ChangeLog 
	ld/testsuite/ld-arm: arm-app-abs32.d arm-app.d arm-lib-plt32.d 
	                     arm-lib.d arm-pic-veneer.d armthumb-lib.d 
	                     farcall-mixed-app-v5.d farcall-mixed-app.d 
	                     farcall-mixed-lib.d group-relocs.d 
	                     mixed-app-v5.d mixed-app.d mixed-lib.d 
	                     thumb2-bl-undefweak.d 

Log message:
	PR 10288
	* arm-dis.c (enum opcode_sentinels): New:  Used to mark the
	boundary between variaant and generic coprocessor instuctions.
	(coprocessor): Use it.
	Fix architecture version of MCRR and MRRC instructions.
	(arm_opcdes): Fix patterns for STRB and STRH instructions.
	(print_insn_coprocessor): Check architecture and extension masks.
	Print a hexadecimal version of any decimal constant that is
	outside of the range of -16 to +32.
	(print_arm_address): Add a return value of the offset used in the
	adress, if it is worth printing a hexadecimal version of it.
	(print_insn_neon): Print a hexadecimal version of any decimal
	constant that is outside of the range of -16 to +32.
	(print_insn_arm): Likewise.
	(print_insn_thumb16): Likewise.
	(print_insn_thumb32): Likewise.
	
	PR 10297
	* arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description
	of an undefined instruction.
	(arm_opcodes): Use it.
	(thumb_opcod): Use it.
	(thumb32_opc): Use it.
	
	Update expected disassembly regrexps in GAS and LD testsuites.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1409&r2=1.1410
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.98&r2=1.99
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1496&r2=1.1497
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch6zk.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch7.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arm-it-auto-2.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arm-it-auto.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/copro.d.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/float.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/fpa-mem.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/group-reloc-ldc.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/group-reloc-ldr.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/iwmmxt.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/maverick.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/neon-omit.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/svc.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb-eabi.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb.d.diff?cvsroot=src&r1=1.11&r2=1.12
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb1_unified.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_add.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_relax.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb32.d.diff?cvsroot=src&r1=1.30&r2=1.31
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp-neon-syntax.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp1xD.d.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp1xD_t2.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfpv3-const-conv.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/xscale.d.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1118&r2=1.1119
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-app-abs32.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-app.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-lib-plt32.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-lib.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-pic-veneer.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/armthumb-lib.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-mixed-app-v5.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-mixed-app.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-mixed-lib.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/group-relocs.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/mixed-app-v5.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/mixed-app.d.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/mixed-lib.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/thumb2-bl-undefweak.d.diff?cvsroot=src&r1=1.1&r2=1.2

Comment 22 Nick Clifton 2009-06-29 08:35:16 IST
Hi Chris,

  Right - I have checked in the patch as it stands at the moment
(pr10288.patch.3).  I will not close this PR though.  I am going to look at the
new problems you have raised today and, I hope, create a new PR.  It was just
annoying to have to keep such a large patch going, especially when it conflicts
with PR 10297.

Cheers
  Nick
Comment 23 cvs-commit@gcc.gnu.org 2009-06-30 11:57:25 IST
Subject: Bug 10288

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2009-06-30 11:57:06

Modified files:
	opcodes        : ChangeLog arm-dis.c 
	gas/testsuite  : ChangeLog 
	gas/testsuite/gas/arm: adrl.d arch4t-eabi.d arch4t.d arch6zk.d 
	                       archv6t2.d arm-it.d arm3.d arm7dm.d 
	                       arm7t.d backslash-at.d bl-local-v4t.d 
	                       blx-local.d copro.d el_segundo.d float.d 
	                       fp-save.d fpa-mem.d group-reloc-alu.d 
	                       group-reloc-ldr.d group-reloc-ldrs.d 
	                       immed.d inst.d iwmmxt.d ldconst.d 
	                       macro1.d mapmisc.d mapsecs.d 
	                       mapshort-eabi.d mapshort-elf.d 
	                       movw-local.d neon-ldst-rm.d offset.d 
	                       reg-alias.d relax_load_align.d tcompat.d 
	                       tcompat2.d thumb-eabi.d thumb.d 
	                       thumb1_unified.d thumb2_add.d thumb2_it.d 
	                       thumb2_it_auto.d thumb2_pool.d 
	                       thumb2_relax.d thumb32.d thumbv6.d 
	                       thumbv6k.d tls.d vfp1.d vfp1_t2.d 
	                       vfp1xD.d wince.d wince_inst.d xscale.d 
	ld/testsuite   : ChangeLog 
	ld/testsuite/ld-arm: arm-app-abs32.d arm-app.d arm-be8.d 
	                     arm-call.d arm-lib-plt32.d arm-lib.d 
	                     arm-movwt.d arm-pic-veneer.d armthumb-lib.d 
	                     armv4-bx.d cortex-a8-fix-b-rel-arm.d 
	                     farcall-mixed-app-v5.d farcall-mixed-app.d 
	                     farcall-mixed-lib.d 
	                     farcall-thumb-arm-pic-veneer.d 
	                     farcall-thumb-arm-short.d 
	                     farcall-thumb-arm.d 
	                     farcall-thumb-thumb-m-pic-veneer.d 
	                     farcall-thumb-thumb-m.d 
	                     farcall-thumb-thumb-pic-veneer.d 
	                     farcall-thumb-thumb.d group-relocs.d 
	                     mixed-app-v5.d mixed-app.d mixed-lib.d 
	                     movw-merge.d thumb2-b-interwork.d tls-app.d 
	                     tls-lib.d 

Log message:
	PR 10288
	* arm-dis.c (coprocessor): Print the LDC and STC versions of the
	LFM and SFM instructions as comments,.
	Improve consistency of formatting for instructions displayed as
	comments and decimal values displayed with their hexadecimal
	equivalents.
	Formatting tidy ups.
	
	Updated expected disassembler regexps.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1410&r2=1.1411
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.99&r2=1.100
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1497&r2=1.1498
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/adrl.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch4t-eabi.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch4t.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch6zk.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/archv6t2.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arm-it.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arm3.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arm7dm.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arm7t.d.diff?cvsroot=src&r1=1.15&r2=1.16
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/backslash-at.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/bl-local-v4t.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/blx-local.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/copro.d.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/el_segundo.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/float.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/fp-save.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/fpa-mem.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/group-reloc-alu.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/group-reloc-ldr.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/group-reloc-ldrs.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/immed.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/inst.d.diff?cvsroot=src&r1=1.17&r2=1.18
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/iwmmxt.d.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/ldconst.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/macro1.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/mapmisc.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/mapsecs.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/mapshort-eabi.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/mapshort-elf.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/movw-local.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/neon-ldst-rm.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/offset.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/reg-alias.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/relax_load_align.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/tcompat.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/tcompat2.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb-eabi.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb.d.diff?cvsroot=src&r1=1.12&r2=1.13
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb1_unified.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_add.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_it.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_it_auto.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_pool.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb2_relax.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb32.d.diff?cvsroot=src&r1=1.31&r2=1.32
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumbv6.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumbv6k.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/tls.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp1.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp1_t2.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/vfp1xD.d.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/wince.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/wince_inst.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/xscale.d.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1119&r2=1.1120
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-app-abs32.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-app.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-be8.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-call.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-lib-plt32.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-lib.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-movwt.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/arm-pic-veneer.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/armthumb-lib.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/armv4-bx.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-mixed-app-v5.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-mixed-app.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-mixed-lib.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-arm-short.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-arm.d.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/farcall-thumb-thumb.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/group-relocs.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/mixed-app-v5.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/mixed-app.d.diff?cvsroot=src&r1=1.10&r2=1.11
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/mixed-lib.d.diff?cvsroot=src&r1=1.7&r2=1.8
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/movw-merge.d.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/thumb2-b-interwork.d.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/tls-app.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-arm/tls-lib.d.diff?cvsroot=src&r1=1.5&r2=1.6

Comment 24 Nick Clifton 2009-06-30 11:58:15 IST
Created attachment 4030 [details]
More disassembly consistency improvements
Comment 25 Nick Clifton 2009-06-30 12:03:41 IST
Hi Chris,

  Right, I have checked in the (uploaded) patch to further improve the
consistency of the disassembler's output.

  With regard to LFM and SFM I do still think that they should disassembled and
displayed as they currently are, even if the architecture has been set to one
that *might* not support them.  In the spirit of compromise however I have added
the LDC and STC versions of the instructions as comments in the disassembler's
output.

  So for example disassembling the binary values that have been mentioned in
this issue, I now get:

   0:   4c585ee5        ldclmi  14, cr5, [r8], {229}    ; 0xe5
   4:   01a23597        undefined instruction 0x01a23597
   8:   3d9da24e        lfmcc   f2, 1, [sp, #312]       ; (ldccc 2, cr10, [sp,
#312])   ; 0x138
   c:   46647659        strbmi  r7, [r4], -r9, asr r6
  10:   77c1cdb4        strbvc  ip, [r1, r4, lsr sp]
  14:   e640361f        strb    r3, [r0], -pc, lsl r6
  18:   4c585ee5        ldclmi  14, cr5, [r8], {229}    ; 0xe5
  1c:   d446399e        strble  r3, [r6], #-2462        ; 0x99e
  20:   11d87ed1        ldrsbne r7, [r8, #225]  ; 0xe1
  24:   44afa697        strtmi  sl, [pc], #1687 ; 2c <foo+0x2c>
  28:   d4bf78b4        ldrtle  r7, [pc], #2228 ; 30 <foo+0x30>
  2c:   bc041350        stclt   3, cr1, [r4], {80}      ; 0x50

Cheers
  Nick
Comment 26 Chris Seberino 2009-06-30 20:22:34 IST
I couldn't apply tc-arm.c.patch but it looked like you applied it already to 
binutils-2.19.51.tar.bz2.  So these comments pertain to your June 30th 2.19.51...

I'll mention 2 things in this paragraph that if you don't want to fix I'm ok
with..There were still some inconsistencies with some hex equivalents that were
missing.  Also, some undefineds that were "undefined instuction 0x...." and
others that were "undefined".   (If you just want to cut out hex equivalents
that ok by me.  Also, objdump already shows the instruction and address so if
you want to just make all undefined's just print "undefined" that is ok with me
too.)

More importantly, it looks like you reintroduced DSP instructions and
instructions for later CPU architectures that don't belong in ARM7TDMI like...
mrrc, blx and ldc2.

There was also some unidentifiable instructions I didn't know what to make of
like these...
usat, movw, vdupcs.8 and fldmdbxmi.
Comment 27 Nick Clifton 2009-07-02 16:40:15 IST
Subject: Re:  "objdump -D --target=binary -m arm7tdmi"
 shows	non-ARM7TDMI instructions

Hi Chris,

> More importantly, it looks like you reintroduced DSP instructions and
> instructions for later CPU architectures that don't belong in ARM7TDMI like...
> mrrc, blx and ldc2.

Are you sure ?  I could not reproduce these.

> There was also some unidentifiable instructions I didn't know what to make of
> like these...
> usat, movw, vdupcs.8 and fldmdbxmi.

According to the "ARMv7-M Architecture Application Level Reference 
Manual" the first one is:

   USAT
   Unsigned Saturate saturates an optionally-shifted signed value
   to a selected unsigned range.
   The Q flag is set if the operation saturates.

   Encoding T1          ARMv6T2, ARMv7
   USAT<c> <Rd>,#<imm5>,<Rn>{,<shift>}

MOVW appears to be an alias for the ARM V6T2 16-bit immediate register 
load instruction:  MOV[WT]{cond} Rd, #<imm16>.

VDUP is a Neon register transfer instruction.

FLDMDBX is a deprecated VFP V1xD (single precision) memory transfer 
instruction.

Cheers
   Nick
Comment 28 Chris Seberino 2009-07-02 17:28:36 IST
(In reply to comment #27)
> Subject: Re:  "objdump -D --target=binary -m arm7tdmi"
>  shows	non-ARM7TDMI instructions
> 
> Hi Chris,
> 
> > More importantly, it looks like you reintroduced DSP instructions and
> > instructions for later CPU architectures that don't belong in ARM7TDMI like...
> > mrrc, blx and ldc2.
> 
> Are you sure ?  I could not reproduce these.

Try these...

4c585ee5 	mrrcmi	14, 14, r5, r8, cr5
fd37a04f 	ldc2	0, cr10, [r7, #-316]!
fabf5236 	blx	0xfefd49dc

(By the way, I didn't apply your latest patch tc0arn.c.patch because it looked
like you already applied it to latest iteration of 2.19.51.)

> > There was also some unidentifiable instructions I didn't know what to make of
> > like these...
> > usat, movw, vdupcs.8 and fldmdbxmi.
> 
> According to the "ARMv7-M Architecture Application Level Reference 
> Manual" the first one is:
> 
>    USAT
>    Unsigned Saturate saturates an optionally-shifted signed value
>    to a selected unsigned range.
>    The Q flag is set if the operation saturates.
> 
>    Encoding T1          ARMv6T2, ARMv7
>    USAT<c> <Rd>,#<imm5>,<Rn>{,<shift>}
> 
> MOVW appears to be an alias for the ARM V6T2 16-bit immediate register 
> load instruction:  MOV[WT]{cond} Rd, #<imm16>.

I wonder if you are making the same mistake I used to.  ARM version numbering is
confusing because there are architecture versions and architecture
*implementation* versions.  ARM7TDMI is an implementation of the ARMv4T
architecture.  The "7" in ARM7TDMI might make one think it support ARMv6 and
ARMv7 but it does NOT.  This is because the architecture version is the old
ARMv4T.  Hence, the above ARMv6 and ARMv7 instructions shouldn't be there form
-m arm7tdmi.

Clear?

P.S. I'm committed to hanging in there until this is as right as you are willing
to make it.  I appreciate all your help.  
Comment 29 Chris Seberino 2009-07-03 06:10:53 IST
I just rebuilt latest binutils Th 7/2/09 evening PST and it seems better now.  I
don't know if you fixed something in the interim or I blew it in my last test.

The only problem that is still around is the undocumented addressing mode for
strb......


46647659 	strbmi	r7, [r4], -r9, asr r6
77c1cdb4 	strbvc	ip, [r1, r4, lsr sp]
e640361f 	strb	r3, [r0], -pc, lsl r6

Did you mean to add the standard general coprocessor instruction as a comment
after the version you preferred?  Because for

3d9da24e 	lfmcc	f2, 1, [sp, #312]

I didn't see a comment with "; ldccc	2, cr10, [sp, #312]"

cs
Comment 30 Chris Seberino 2009-07-03 19:26:41 IST
> I didn't see a comment with "; ldccc	2, cr10, [sp, #312]"

Nick

I owe you an apology.  I do see this comment.  The only lingering problem is the
strb nonexistent addressing mode.  

I will now start comprehensive brute force testing of your code.  What I mean by
that is that there are "only" 2^32 possible 32 bit instructions.  I plan to
compare the output of my disassembler against objdump for all those guys. 
Results to follow soon.  Then we can be happy we did extensive testing and all
we practically could to get objdump done right for the world! :)

cs

Comment 31 Nick Clifton 2009-07-07 14:44:02 IST
Created attachment 4042 [details]
Catch unexpected STRB scaled addressing modes
Comment 32 Nick Clifton 2009-07-07 14:45:06 IST
Hi Chris,

  I have uploaded another patch which should take care of the bogus STRB
addressing modes.  I will be checking it into the mainline sources shortly.

Cheers
  Nick
Comment 33 cvs-commit@gcc.gnu.org 2009-07-07 14:46:32 IST
Subject: Bug 10288

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2009-07-07 14:46:14

Modified files:
	opcodes        : ChangeLog arm-dis.c 

Log message:
	PR 10288
	* arm-dis.c (arm_opcodes): Be more strict about decoding scaled
	addressing modes.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1413&r2=1.1414
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.100&r2=1.101

Comment 34 Chris Seberino 2009-07-07 17:41:07 IST
Nick,

I'm very glad you are still sending patches on this.  I very much appreciate it.
 We are almost done....

I was afraid this would happen.  It seems for some reason often when we try to
fix something unrelated to the "DSP and newer instructions bug" that that old
bug keeps sneaking back in.

The 6/30 patch was wonderful because the *only* leftover issue was the STRB
scaled addressing modes.

Unfortunately, I must report that once again we need to remove instructions that
don't belong like mrrc, blx, ldc2, usat, etc.

You can pat yourself on the back because the current state of binutils is
beautiful and almost across the finish line.  All you need to do is take another
crack at a new patch to it and we'll be golden.

chris  
Comment 35 Nick Clifton 2009-07-10 08:21:20 IST
Hi Chris,

> Unfortunately, I must report that once again we need to remove instructions 
> that don't belong like mrrc, blx, ldc2, usat, etc.

I am still not seeing this.  You will have to show me a way to reproduce the effect.

Not for reference this is what I am currently seeing with my local test case:

  % cat 10288.s

        .text
  foo:
        .word 0x4c585ee5
        .word 0x01a23597
        .word 0x3d9da24e
        .word 0x46647659
        .word 0x77c1cdb4
        .word 0xe640361f
        .word 0x4c585ee5
        .word 0xd446399e
        .word 0x11d87ed1
        .word 0x44afa697
        .word 0xd4bf78b4
        .word 0xbc041350
        nop
        .word 0x4c585ee5
        .word 0xfd37a04f
        .word 0xfabf5236
        .word 0x46647659    @    strbmi  r7, [r4], -r9, asr r6
        .word 0x77c1cdb4    @    strbvc  ip, [r1, r4, lsr sp]
        .word 0xe640361f    @    strb    r3, [r0], -pc, lsl r6
        .word 0x3d9da24e    @    lfmcc   f2, 1, [sp, #312]

  % arm-eabi-as 10288.s -o 10288.o
  % arm-eabi-objdump -D -j .text -marm7tdmi 10288.o

   0:   4c585ee5        ldclmi  14, cr5, [r8], {229}    ; 0xe5
   4:   01a23597        undefined instruction 0x01a23597
   8:   3d9da24e        lfmcc   f2, 1, [sp, #312]       ; (ldccc 2, cr10, [sp,
#312])   ; 0x138
   c:   46647659        undefined instruction 0x46647659
  10:   77c1cdb4        undefined instruction 0x77c1cdb4
  14:   e640361f        undefined instruction 0xe640361f
  18:   4c585ee5        ldclmi  14, cr5, [r8], {229}    ; 0xe5
  1c:   d446399e        strble  r3, [r6], #-2462        ; 0x99e
  20:   11d87ed1        ldrsbne r7, [r8, #225]  ; 0xe1
  24:   44afa697        strtmi  sl, [pc], #1687 ; 2c <foo+0x2c>
  28:   d4bf78b4        ldrtle  r7, [pc], #2228 ; 30 <foo+0x30>
  2c:   bc041350        stclt   3, cr1, [r4], {80}      ; 0x50
  30:   e1a00000        nop                     ; (mov r0, r0)
  34:   4c585ee5        ldclmi  14, cr5, [r8], {229}    ; 0xe5
  38:   fd37a04f        undefined instruction 0xfd37a04f
  3c:   fabf5236        undefined instruction 0xfabf5236
  40:   46647659        undefined instruction 0x46647659
  44:   77c1cdb4        undefined instruction 0x77c1cdb4
  48:   e640361f        undefined instruction 0xe640361f
  4c:   3d9da24e        lfmcc   f2, 1, [sp, #312]       ; (ldccc 2, cr10, [sp,
#312])   ; 0x138

  % arm-eabi-objdump -D -j .text 10288.o

   0:   4c585ee5        mrrcmi  14, 14, r5, r8, cr5
   4:   01a23597        undefined instruction 0x01a23597
   8:   3d9da24e        lfmcc   f2, 1, [sp, #312]       ; (ldccc 2, cr10, [sp,
#312])   ; 0x138
   c:   46647659        undefined instruction 0x46647659
  10:   77c1cdb4        undefined instruction 0x77c1cdb4
  14:   e640361f        undefined instruction 0xe640361f
  18:   4c585ee5        mrrcmi  14, 14, r5, r8, cr5
  1c:   d446399e        strble  r3, [r6], #-2462        ; 0x99e
  20:   11d87ed1        ldrsbne r7, [r8, #225]  ; 0xe1
  24:   44afa697        strtmi  sl, [pc], #1687 ; 2c <foo+0x2c>
  28:   d4bf78b4        ldrtle  r7, [pc], #2228 ; 30 <foo+0x30>
  2c:   bc041350        stclt   3, cr1, [r4], {80}      ; 0x50
  30:   e1a00000        nop                     ; (mov r0, r0)
  34:   4c585ee5        mrrcmi  14, 14, r5, r8, cr5
  38:   fd37a04f        ldc2    0, cr10, [r7, #-316]!   ; 0xfffffec4
  3c:   fabf5236        blx     fefd491c <foo+0xfefd491c>
  40:   46647659        undefined instruction 0x46647659
  44:   77c1cdb4        undefined instruction 0x77c1cdb4
  48:   e640361f        undefined instruction 0xe640361f
  4c:   3d9da24e        lfmcc   f2, 1, [sp, #312]       ; (ldccc 2, cr10, [sp,
#312])   ; 0x138


Cheers
  Nick

Comment 36 Chris Seberino 2009-07-10 18:46:23 IST
Nick

Sorry this is the second time I sent out a false alarm.  My guess is there is
some lag time between when your email notice arrives in my mailbox and the new
tarballs get posted.  Hence, I end up pulling an old tarball and then few days
later all works fine with a newer tarball.

ALL my previous preliminary tests now pass on
binutils-2.19.51.tar.bz2 with the md5sum of 572abc9d57659cae8b2654217f642cb4.

Now I will start comprehensive testing of all 4 billions instructions and get
back to you in a few days with the final output of that battery of tests.

Good job!

Chris


Comment 37 Chris Seberino 2009-07-11 06:22:15 IST
OK.  Here is first bug from the serious testing....

"000000b0 	strheq	r0, [r0], r0"

That should be "strheq	r0, [r0], -r0" <--- notice the negative

cs
Comment 38 Chris Seberino 2009-07-11 06:33:12 IST
I think all of the following are wrong.  This "asr" part of addressing mode must
be instructions like 0x0000005Z for Z=0,1,2,3, ...

*not* 0x000000dZ. <--- notice the "d".


<      340:	000000d0 	andeq	r0, r0, r0, asr r0
<      344:	000000d1 	andeq	r0, r0, r1, asr r0
<      348:	000000d2 	andeq	r0, r0, r2, asr r0
<      34c:	000000d3 	andeq	r0, r0, r3, asr r0
<      350:	000000d4 	andeq	r0, r0, r4, asr r0
<      354:	000000d5 	andeq	r0, r0, r5, asr r0
<      358:	000000d6 	andeq	r0, r0, r6, asr r0
<      35c:	000000d7 	andeq	r0, r0, r7, asr r0
<      360:	000000d8 	andeq	r0, r0, r8, asr r0
<      364:	000000d9 	andeq	r0, r0, r9, asr r0
<      368:	000000da 	andeq	r0, r0, sl, asr r0
<      36c:	000000db 	andeq	r0, r0, fp, asr r0
<      370:	000000dc 	andeq	r0, r0, ip, asr r0
<      374:	000000dd 	andeq	r0, r0, sp, asr r0
<      378:	000000de 	andeq	r0, r0, lr, asr r0
<      37c:	000000df 	andeq	r0, r0, pc, asr r0
Comment 39 Chris Seberino 2009-07-11 06:37:49 IST
I think all of the following are wrong.  This "ror" part of addressing mode 1 must
be instructions like 0x0000007Z for Z=0,1,2,3, ...

*not* 0x000000fZ. <--- notice the "f".


<      3c0:	000000f0 	andeq	r0, r0, r0, ror r0
<      3c4:	000000f1 	andeq	r0, r0, r1, ror r0
<      3c8:	000000f2 	andeq	r0, r0, r2, ror r0
<      3cc:	000000f3 	andeq	r0, r0, r3, ror r0
<      3d0:	000000f4 	andeq	r0, r0, r4, ror r0
<      3d4:	000000f5 	andeq	r0, r0, r5, ror r0
<      3d8:	000000f6 	andeq	r0, r0, r6, ror r0
<      3dc:	000000f7 	andeq	r0, r0, r7, ror r0
<      3e0:	000000f8 	andeq	r0, r0, r8, ror r0
<      3e4:	000000f9 	andeq	r0, r0, r9, ror r0
<      3e8:	000000fa 	andeq	r0, r0, sl, ror r0
<      3ec:	000000fb 	andeq	r0, r0, fp, ror r0
<      3f0:	000000fc 	andeq	r0, r0, ip, ror r0
<      3f4:	000000fd 	andeq	r0, r0, sp, ror r0
<      3f8:	000000fe 	andeq	r0, r0, lr, ror r0
<      3fc:	000000ff 	andeq	r0, r0, pc, ror r0
Comment 40 cvs-commit@gcc.gnu.org 2009-07-14 14:17:10 IST
Subject: Bug 10288

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2009-07-14 14:16:35

Modified files:
	opcodes        : ChangeLog arm-dis.c 

Log message:
	PR 10288
	* arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1
	patterns.
	(arm_decode_shift): Catch illegal register based shifts.
	(print_insn_arm): Properly handle negative register r0
	post-indexed addressing.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1417&r2=1.1418
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.103&r2=1.104

Comment 41 Nick Clifton 2009-07-14 14:17:33 IST
Created attachment 4052 [details]
Addressing mode fixes
Comment 42 Nick Clifton 2009-07-14 14:20:55 IST
Hi Chris,

> My guess is there is some lag time between when your email notice arrives in 
> my mailbox and the new tarballs get posted.

True - it is an automatic script that only runs once a day.  For faster access
to the changes I would recommend checking the sources out of the repository
using CVS.

> "000000b0 	strheq	r0, [r0], r0"

> *not* 0x000000dZ. <--- notice the "d".

These are both fixed with the latest patch (uploaded as pr10288.patch.5 and
checked into the repository).

Cheers
  Nick


Comment 43 Chris Seberino 2009-07-16 18:16:11 IST
Nick

Many bit regions in ARM instructions are specified as SBZ "Should Be Zero".

ARM docs say if these bits are NOT zero that the results are UNPREDICTABLE for
all ARM chips!

So the question is what is the best thing for objdump to do in these situations
where a bit region is not zeroed out when it should be.

I think the cleanest thing to do is to return UNDEFINED.  I found some incorrect
ldrsb's and ldrsh's that I think would best be interpreted as UNDEFINED instead....

Here are some examples. (These all have SBZ regions that aren't zeroed out)...
<    2fe40:	001001d0 	ldrsbeq	r0, [r0], -r0
<    2fe44:	001001d1 	ldrsbeq	r0, [r0], -r1
<    2fe48:	001001d2 	ldrsbeq	r0, [r0], -r2
<    2fe4c:	001001d3 	ldrsbeq	r0, [r0], -r3
<    2fe50:	001001d4 	ldrsbeq	r0, [r0], -r4
<    2fe54:	001001d5 	ldrsbeq	r0, [r0], -r5
<    2fe58:	001001d6 	ldrsbeq	r0, [r0], -r6
<    2fe5c:	001001d7 	ldrsbeq	r0, [r0], -r7
<    2fe60:	001001d8 	ldrsbeq	r0, [r0], -r8
<    2fe64:	001001d9 	ldrsbeq	r0, [r0], -r9

<    2fec0:	001001f0 	ldrsheq	r0, [r0], -r0
<    2fec4:	001001f1 	ldrsheq	r0, [r0], -r1
<    2fec8:	001001f2 	ldrsheq	r0, [r0], -r2
<    2fecc:	001001f3 	ldrsheq	r0, [r0], -r3
<    2fed0:	001001f4 	ldrsheq	r0, [r0], -r4
<    2fed4:	001001f5 	ldrsheq	r0, [r0], -r5
<    2fed8:	001001f6 	ldrsheq	r0, [r0], -r6

...etc.

Would it be hard for you to make these return UNDEFINED?

cs
Comment 44 Chris Seberino 2009-07-16 18:44:16 IST
Nick

If you think the SBZ issue isn't worth changing, or fine the way it is, that is
fine.  I'll move on.  I just wanted to make you aware of what I found.  That's all.

cs
Comment 45 cvs-commit@gcc.gnu.org 2009-07-20 12:11:33 IST
Subject: Bug 10288

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2009-07-20 12:11:18

Modified files:
	opcodes        : ChangeLog arm-dis.c 

Log message:
	PR 10288
	* arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register
	offset or indexed based addressing mode 3.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1418&r2=1.1419
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.104&r2=1.105

Comment 46 Nick Clifton 2009-07-20 12:16:02 IST
Hi Chris,

  OK, I have checked in a patch to handle the SBZ field in addressing mode 3.

Cheers
  Nick
Comment 47 Chris Seberino 2009-08-04 17:03:30 IST
Nick

Would it be possible for me to take a few weeks break from our work on

http://sourceware.org/bugzilla/show_bug.cgi?id=10288

and come back to it?  Other things came up in the short term and these last few
bugs are a little trickier than the early more obvious ones.  I'd like to rest
for a bit doing other things and then come back.  I don't know if you want to
close this ticket for
now or leave it open until I return.

I just don't want you to think I'm bailing on this.

Chris

Comment 48 Gilbie Rivas 2015-10-06 13:15:14 IST
Practical analysis - I learned a lot from the information ! Does anyone know if I can obtain a template ARMV7 example to type on?
Comment 49 chastity red 2015-10-13 20:20:41 IST
Greetings Gilbie! My assistant filled out a ARMV7  form document at this place:  http://goo.gl/Ms4ebj