The following table lists all available RISC-V specific options.
Generate position-independent code
Don’t generate position-independent code (default)
Select the base isa, as specified by ISA. For example -march=rv32ima. If this option and the architecture attributes aren’t set, then assembler will check the default configure setting –with-arch=ISA.
Select the default isa spec version. If the version of ISA isn’t set by -march, then assembler helps to set the version according to the default chosen spec. If this option isn’t set, then assembler will check the default configure setting –with-isa-spec=ISAspec.
Select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren’t set, then assembler will check the default configure setting –with-priv-spec=PRIVspec.
Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI).
Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default)
Don’t do linker relaxations.
Generate the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.
Don’t generate the default riscv elf attribute section if the .attribute directives are not set.
Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions.
Don’t do CSR checking.
Generate code for a little endian machine.
Generate code for a big endian machine.