Here is a brief summary of how to invoke
as. For details,
see Command-Line Options.
as [-a[cdghlns][=file]] [–alternate] [-D] [–compress-debug-sections] [–nocompress-debug-sections] [–debug-prefix-map old=new] [–defsym sym=val] [-f] [-g] [–gstabs] [–gstabs+] [–gdwarf-<N>] [–gdwarf-sections] [–gdwarf-cie-version=VERSION] [–help] [-I dir] [-J] [-K] [-L] [–listing-lhs-width=NUM] [–listing-lhs-width2=NUM] [–listing-rhs-width=NUM] [–listing-cont-lines=NUM] [–keep-locals] [–no-pad-sections] [-o objfile] [-R] [–statistics] [-v] [-version] [–version] [-W] [–warn] [–fatal-warnings] [-w] [-x] [-Z] [@FILE] [–sectname-subst] [–size-check=[error|warning]] [–elf-stt-common=[no|yes]] [–generate-missing-build-notes=[no|yes]] [–target-help] [target-options] [–|files …] Target AArch64 options: [-EB|-EL] [-mabi=ABI] Target Alpha options: [-mcpu] [-mdebug | -no-mdebug] [-replace | -noreplace] [-relax] [-g] [-Gsize] [-F] [-32addr] Target ARC options: [-mcpu=cpu] [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] [-mcode-density] [-mrelax] [-EB|-EL] Target ARM options: [-mcpu=processor[+extension…]] [-march=architecture[+extension…]] [-mfpu=floating-point-format] [-mfloat-abi=abi] [-meabi=ver] [-mthumb] [-EB|-EL] [-mapcs-32|-mapcs-26|-mapcs-float| -mapcs-reentrant] [-mthumb-interwork] [-k] Target Blackfin options: [-mcpu=processor[-sirevision]] [-mfdpic] [-mno-fdpic] [-mnopic] Target BPF options: [-EL] [-EB] Target CRIS options: [–underscore | –no-underscore] [–pic] [-N] [–emulation=criself | –emulation=crisaout] [–march=v0_v10 | –march=v10 | –march=v32 | –march=common_v10_v32] Target C-SKY options: [-march=arch] [-mcpu=cpu] [-EL] [-mlittle-endian] [-EB] [-mbig-endian] [-fpic] [-pic] [-mljump] [-mno-ljump] [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr] [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr] [-mnolrw ] [-mno-lrw] [-melrw] [-mno-elrw] [-mlaf ] [-mliterals-after-func] [-mno-laf] [-mno-literals-after-func] [-mlabr] [-mliterals-after-br] [-mno-labr] [-mnoliterals-after-br] [-mistack] [-mno-istack] [-mhard-float] [-mmp] [-mcp] [-mcache] [-msecurity] [-mtrust] [-mdsp] [-medsp] [-mvdsp] Target D10V options: [-O] Target D30V options: [-O|-n|-N] Target EPIPHANY options: [-mepiphany|-mepiphany16] Target H8/300 options: [-h-tick-hex] Target i386 options: [–32|–x32|–64] [-n] [-march=CPU[+EXTENSION…]] [-mtune=CPU] Target IA-64 options: [-mconstant-gp|-mauto-pic] [-milp32|-milp64|-mlp64|-mp64] [-mle|mbe] [-mtune=itanium1|-mtune=itanium2] [-munwind-check=warning|-munwind-check=error] [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] [-x|-xexplicit] [-xauto] [-xdebug] Target IP2K options: [-mip2022|-mip2022ext] Target M32C options: [-m32c|-m16c] [-relax] [-h-tick-hex] Target M32R options: [–m32rx|–[no-]warn-explicit-parallel-conflicts| –W[n]p] Target M680X0 options: [-l] [-m68000|-m68010|-m68020|…] Target M68HC11 options: [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] [-mshort|-mlong] [-mshort-double|-mlong-double] [–force-long-branches] [–short-branches] [–strict-direct-mode] [–print-insn-syntax] [–print-opcodes] [–generate-example] Target MCORE options: [-jsri2bsr] [-sifilter] [-relax] [-mcpu=[210|340]] Target Meta options: [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options: Target MIPS options: [-nocpp] [-EL] [-EB] [-O[optimization level]] [-g[debug level]] [-G num] [-KPIC] [-call_shared] [-non_shared] [-xgot [-mvxworks-pic] [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] [-mfp64] [-mgp64] [-mfpxx] [-modd-spreg] [-mno-odd-spreg] [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] [-mips64r3] [-mips64r5] [-mips64r6] [-construct-floats] [-no-construct-floats] [-mignore-branch-isa] [-mno-ignore-branch-isa] [-mnan=encoding] [-trap] [-no-break] [-break] [-no-trap] [-mips16] [-no-mips16] [-mmips16e2] [-mno-mips16e2] [-mmicromips] [-mno-micromips] [-msmartmips] [-mno-smartmips] [-mips3d] [-no-mips3d] [-mdmx] [-no-mdmx] [-mdsp] [-mno-dsp] [-mdspr2] [-mno-dspr2] [-mdspr3] [-mno-dspr3] [-mmsa] [-mno-msa] [-mxpa] [-mno-xpa] [-mmt] [-mno-mt] [-mmcu] [-mno-mcu] [-mcrc] [-mno-crc] [-mginv] [-mno-ginv] [-mloongson-mmi] [-mno-loongson-mmi] [-mloongson-cam] [-mno-loongson-cam] [-mloongson-ext] [-mno-loongson-ext] [-mloongson-ext2] [-mno-loongson-ext2] [-minsn32] [-mno-insn32] [-mfix7000] [-mno-fix7000] [-mfix-rm7000] [-mno-fix-rm7000] [-mfix-vr4120] [-mno-fix-vr4120] [-mfix-vr4130] [-mno-fix-vr4130] [-mfix-r5900] [-mno-fix-r5900] [-mdebug] [-no-mdebug] [-mpdr] [-mno-pdr] Target MMIX options: [–fixed-special-register-names] [–globalize-symbols] [–gnu-syntax] [–relax] [–no-predefined-symbols] [–no-expand] [–no-merge-gregs] [-x] [–linker-allocated-gregs] Target Nios II options: [-relax-all] [-relax-section] [-no-relax] [-EB] [-EL] Target NDS32 options: [-EL] [-EB] [-O] [-Os] [-mcpu=cpu] [-misa=isa] [-mabi=abi] [-mall-ext] [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext] [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div] [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext] [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs] [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax] [-mb2bb] Target PDP11 options: [-mpic|-mno-pic] [-mall] [-mno-extensions] [-mextension|-mno-extension] [-mcpu] [-mmachine] Target picoJava options: [-mb|-me] Target PowerPC options: [-a32|-a64] [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko| -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500| -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x| -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom] [-many] [-maltivec|-mvsx|-mhtm|-mvle] [-mregnames|-mno-regnames] [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] [-msolaris|-mno-solaris] [-nops=count] Target PRU options: [-link-relax] [-mnolink-relax] [-mno-warn-regname-label] Target RISC-V options: [-fpic|-fPIC|-fno-pic] [-march=ISA] [-mabi=ABI] [-mlittle-endian|-mbig-endian] Target RL78 options: [-mg10] [-m32bit-doubles|-m64bit-doubles] Target RX options: [-mlittle-endian|-mbig-endian] [-m32bit-doubles|-m64bit-doubles] [-muse-conventional-section-names] [-msmall-data-limit] [-mpid] [-mrelax] [-mint-register=number] [-mgcc-abi|-mrx-abi] Target s390 options: [-m31|-m64] [-mesa|-mzarch] [-march=CPU] [-mregnames|-mno-regnames] [-mwarn-areg-zero] Target SCORE options: [-EB][-EL][-FIXDD][-NWARN] [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] [-march=score7][-march=score3] [-USE_R1][-KPIC][-O0][-G num][-V] Target SPARC options: [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 -Asparcvisr|-Asparc5] [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 -bump] [-32|-64] [–enforce-aligned-data][–dcti-couples-detect] Target TIC54X options: [-mcpu=54|-mcpu=54lp] [-mfar-mode|-mf] [-merrors-to-file <filename>|-me <filename>] Target TIC6X options: [-march=arch] [-mbig-endian|-mlittle-endian] [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] [-mpic|-mno-pic] Target TILE-Gx options: [-m32|-m64][-EB][-EL] Target Visium options: [-mtune=arch] Target Xtensa options: [–[no-]text-section-literals] [–[no-]auto-litpools] [–[no-]absolute-literals] [–[no-]target-align] [–[no-]longcalls] [–[no-]transform] [–rename-section oldname=newname] [–[no-]trampolines] [–abi-windowed|–abi-call0] Target Z80 options: [-march=CPU[-EXT][+EXT]] [-local-prefix=PREFIX] [-colonless] [-sdcc] [-fp-s=FORMAT] [-fp-d=FORMAT]
Read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed.
Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively.
Turn on listings, in any of a variety of ways:
omit false conditionals
omit debugging directives
include general information, like as version and options passed
include high-level source
include macro expansions
omit forms processing
set the name of the listing file
You may combine these options; for example, use ‘-aln’ for assembly listing without forms processing. The ‘=file’ option, if used, must be the last one. By itself, ‘-a’ defaults to ‘-ahls’.
Begin in alternate macro mode.
Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note if compression would make a given section larger then it is not compressed.
These options control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug sections using zlib. The debug sections are renamed to begin with ‘.zdebug’. Note if compression would make a given section larger then it is not compressed nor renamed.
Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
Ignored. This option is accepted for script compatibility with calls to other assemblers.
When assembling files in directory old, record debugging information describing them as in new instead.
Define the symbol sym to be value before assembling the input file.
value must be an integer constant. As in C, a leading ‘0x’
indicates a hexadecimal value, and a leading ‘0’ indicates an octal
value. The value of the symbol can be overridden inside a source file via the
use of a
“fast”—skip whitespace and comment preprocessing (assume source is compiler output).
Generate debugging information for each assembler source line using whichever
debug format is preferred by the target. This currently means either STABS,
ECOFF or DWARF2. When the debug format is DWARF then a
.debug_line section is only emitted when the assembly file doesn’t
generate one itself.
Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.
Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note—this option is only supported by some targets, not all of them.
This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note - enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note - enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note - enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix.
Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specificed the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4.
Issue an error or warning for invalid ELF .size directive.
These options control whether the ELF assembler should generate common
symbols with the
STT_COMMON type. The default can be controlled
by a configure option --enable-elf-stt-common.
These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the --enable-generate-build-notes configure option.
Print a summary of the command-line options and exit.
Print a summary of all target specific options and exit.
Add directory dir to the search list for
Don’t warn about signed overflow.
Issue warnings when difference tables altered for long displacements.
Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically ‘.L’ for ELF systems or ‘L’ for traditional a.out systems. See Symbol Names.
Set the maximum width, in words, of the output data column for an assembler listing to number.
Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
Set the maximum width of an input source line, as displayed in a listing, to number bytes.
Set the maximum number of lines printed in a listing for a single line of input to number + 1.
Stop the assembler for padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints.
Name the object-file output from
Fold the data section into the text section.
Honor substitution sequences in section names.
Print the maximum space (in bytes) and total time (in seconds) used by assembly.
Remove local absolute symbols from the outgoing symbol table.
as version and exit.
Suppress warning messages.
Treat warnings as errors.
Don’t suppress warning messages or treat them as errors.
Generate an object file even after errors.
-- | files …
Standard input, or source files to assemble.
See AArch64 Options, for the options available when as is configured for the 64-bit mode of the ARM Architecture (AArch64).
See Alpha Options, for the options available when as is configured for an Alpha processor.
The following options are available when as is configured for an ARC processor.
This option selects the core processor variant.
-EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
Enable Code Density extension instructions.
The following options are available when as is configured for the ARM processor family.
Specify which ARM processor variant is the target.
Specify which ARM architecture variant is used by the target.
Select which Floating Point architecture is the target.
Select which floating point ABI is in use.
Enable Thumb only instruction decoding.
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
Select which procedure calling convention is in use.
-EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
Specify that the code has been generated with interworking between Thumb and ARM code in mind.
Turns on CodeComposer Studio assembly syntax compatibility mode.
Specify that PIC code has been generated.
See Blackfin Options, for the options available when as is configured for the Blackfin processor family.
See BPF Options, for the options available when as is configured for the Linux kernel BPF processor family.
See the info pages for documentation of the CRIS-specific options.
See C-SKY Options, for the options available when as is configured for the C-SKY processor family.
The following options are available when as is configured for a D10V processor.
Optimize output by parallelizing instructions.
The following options are available when as is configured for a D30V processor.
Optimize output by parallelizing instructions.
Warn when nops are generated.
Warn when a nop after a 32-bit multiply instruction is generated.
The following options are available when as is configured for the Adapteva EPIPHANY series.
See Epiphany Options, for the options available when as is configured for an Epiphany processor.
See i386-Options, for the options available when as is configured for an i386 processor.
The following options are available when as is configured for the Ubicom IP2K series.
Specifies that the extended IP2022 instructions are allowed.
Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones.
The following options are available when as is configured for the Renesas M32C and M16C processors.
Assemble M32C instructions.
Assemble M16C instructions (the default).
Enable support for link-time relaxations.
Support H’00 style hex constants in addition to 0x00 style.
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
--warn-explicit-parallel-conflicts or --Wp
Produce warning messages when questionable parallel constructs are encountered.
--no-warn-explicit-parallel-conflicts or --Wnp
Do not produce warning messages when questionable parallel constructs are encountered.
The following options are available when as is configured for the Motorola 68000 series.
Shorten references to undefined symbols, to one word instead of two.
-m68000 | -m68008 | -m68010 | -m68020 | -m68030
| -m68040 | -m68060 | -m68302 | -m68331 | -m68332
| -m68333 | -m68340 | -mcpu32 | -m5200
Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.
-m68881 | -m68882 | -mno-68881 | -mno-68882
The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it’s possible to do emulation of the coprocessor instructions with the main processor.
-m68851 | -mno-68851
The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.
See Nios II Options, for the options available when as is configured for an Altera Nios II processor.
For details about the PDP-11 machine dependent features options, see PDP-11-Options.
-mpic | -mno-pic
Generate position-independent (or position-dependent) code. The default is -mpic.
Enable all instruction set extensions. This is the default.
Disable all instruction set extensions.
-mextension | -mno-extension
Enable (or disable) a particular instruction set extension.
Enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
Enable the instruction set extensions supported by a particular machine model, and disable all other extensions.
The following options are available when as is configured for a picoJava processor.
Generate “big endian” format output.
Generate “little endian” format output.
See PRU Options, for the options available when as is configured for a PRU processor.
The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series.
-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg
Specify what processor is the target. The default is defined by the configuration option when building the assembler.
Instruct the linker to offset RAM addresses from S12X address space into XGATE address space.
Specify to use the 16-bit integer ABI.
Specify to use the 32-bit integer ABI.
Specify to use the 32-bit double ABI.
Specify to use the 64-bit double ABI.
Relative branches are turned into absolute ones. This concerns conditional branches, unconditional branches and branches to a sub routine.
-S | --short-branches
Do not turn relative branches into absolute ones when the offset is out of range.
Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode.
Print the syntax of instruction in case of error.
Print the list of instructions with syntax and then exit.
Print an example of instruction for each possible instruction and then exit.
This option is only useful for testing
The following options are available when
as is configured
for the SPARC architecture:
-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av9 | -Av9a
Explicitly select a variant of the SPARC architecture.
‘-Av8plus’ and ‘-Av8plusa’ select a 32 bit environment. ‘-Av9’ and ‘-Av9a’ select a 64 bit environment.
‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with UltraSPARC extensions.
-xarch=v8plus | -xarch=v8plusa
For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
Warn when the assembler switches to another architecture.
The following options are available when as is configured for the ’c54x architecture.
Enable extended addressing mode. All addresses and relocations will assume extended addressing (usually 23 bits).
Sets the CPU version being compiled for.
Redirect error output to a file, for broken systems which don’t support such behaviour in the shell.
The following options are available when as is configured for a MIPS processor.
This option sets the largest size of an object that can be referenced
implicitly with the
gp register. It is only accepted for targets that
use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
Generate “big endian” format output.
Generate “little endian” format output.
Generate code for a particular MIPS Instruction Set Architecture level. ‘-mips1’ is an alias for ‘-march=r3000’, ‘-mips2’ is an alias for ‘-march=r6000’, ‘-mips3’ is an alias for ‘-march=r4000’ and ‘-mips4’ is an alias for ‘-march=r8000’. ‘-mips5’, ‘-mips32’, ‘-mips32r2’, ‘-mips32r3’, ‘-mips32r5’, ‘-mips32r6’, ‘-mips64’, ‘-mips64r2’, ‘-mips64r3’, ‘-mips64r5’, and ‘-mips64r6’ correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively.
Generate code for a particular MIPS CPU.
Schedule and tune for a particular MIPS CPU.
Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
Do not attempt to schedule the preceding instruction into the delay slot
of a branch instruction placed at the end of a short loop of six
instructions or fewer and always schedule a
nop instruction there
instead. The short loop bug under certain conditions causes loops to
execute only once or twice, due to a hardware bug in the R5900 chip.
Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
Control generation of
The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. ‘-mgp32’ controls the size of general-purpose registers and ‘-mfp32’ controls the size of floating-point registers.
The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times. ‘-mgp64’ controls the size of general-purpose registers and ‘-mfp64’ controls the size of floating-point registers.
The register sizes are normally inferred from the ISA and ABI, but using this flag in combination with ‘-mabi=32’ enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide.
Enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. ‘-mfpxx’ implies ‘-mno-odd-spreg’, otherwise the default is ‘-modd-spreg’.
Generate code for the MIPS 16 processor. This is equivalent to putting
.module mips16 at the start of the assembly file. ‘-no-mips16’
turns off this option.
Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
.module mips16e2 at the start of the assembly file.
‘-mno-mips16e2’ turns off this option.
Generate code for the microMIPS processor. This is equivalent to putting
.module micromips at the start of the assembly file.
‘-mno-micromips’ turns off this option. This is equivalent to putting
.module nomicromips at the start of the assembly file.
Enables the SmartMIPS extension to the MIPS32 instruction set. This is
equivalent to putting
.module smartmips at the start of the assembly
file. ‘-mno-smartmips’ turns off this option.
Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. ‘-no-mips3d’ turns off this option.
Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. ‘-no-mdmx’ turns off this option.
Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. ‘-mno-dsp’ turns off this option.
Generate code for the DSP Release 2 Application Specific Extension. This option implies ‘-mdsp’. This tells the assembler to accept DSP Release 2 instructions. ‘-mno-dspr2’ turns off this option.
Generate code for the DSP Release 3 Application Specific Extension. This option implies ‘-mdsp’ and ‘-mdspr2’. This tells the assembler to accept DSP Release 3 instructions. ‘-mno-dspr3’ turns off this option.
Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. ‘-mno-msa’ turns off this option.
Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. ‘-mno-xpa’ turns off this option.
Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. ‘-mno-mt’ turns off this option.
Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. ‘-mno-mcu’ turns off this option.
Generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions. ‘-mno-crc’ turns off this option.
Generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions. ‘-mno-ginv’ turns off this option.
Generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions. ‘-mno-loongson-mmi’ turns off this option.
Generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions. ‘-mno-loongson-cam’ turns off this option.
Generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions. ‘-mno-loongson-ext’ turns off this option.
Generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies ‘-mloongson-ext’. This tells the assembler to accept Loongson EXT2 instructions. ‘-mno-loongson-ext2’ turns off this option.
Only use 32-bit instruction encodings when generating code for the
microMIPS processor. This option inhibits the use of any 16-bit
instructions. This is equivalent to putting
.set insn32 at
the start of the assembly file. ‘-mno-insn32’ turns off this
option. This is equivalent to putting
.set noinsn32 at the
start of the assembly file. By default ‘-mno-insn32’ is
selected, allowing all instructions to be used.
The ‘--no-construct-floats’ option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default ‘--construct-floats’ is selected, allowing construction of these floating point constants.
The ‘--relax-branch’ option enables the relaxation of out-of-range branches. By default ‘--no-relax-branch’ is selected, causing any out-of-range branches to produce an error.
Ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch’s target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match. ‘-mignore-branch-isa’ disables these checks. By default ‘-mno-ignore-branch-isa’ is selected, causing any invalid branch requiring a transition between ISA modes to produce an error.
Select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default.
This option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility.
The available configuration names are: ‘mipself’, ‘mipslelf’ and ‘mipsbelf’. Choosing ‘mipself’ now has no effect, since the output is always ELF. ‘mipslelf’ and ‘mipsbelf’ select little- and big-endian output respectively, but ‘-EL’ and ‘-EB’ are now the preferred options instead.
as ignores this option. It is accepted for compatibility with
the native tools.
Control how to deal with multiplication overflow and division by zero. ‘--trap’ or ‘--no-break’ (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); ‘--break’ or ‘--no-trap’ (also synonyms, and the default) take a break exception.
When this option is used,
as will issue a warning every
time it generates a nop instruction from a macro.
The following options are available when as is configured for an MCore processor.
Enable or disable the JSRI to BSR transformation. By default this is enabled. The command-line option ‘-nojsri2bsr’ can be used to disable it.
Enable or disable the silicon filter behaviour. By default this is disabled. The default can be overridden by the ‘-sifilter’ command-line option.
Alter jump instructions for long displacements.
Select the cpu type on the target hardware. This controls which instructions can be assembled.
Assemble for a big endian target.
Assemble for a little endian target.
See Meta Options, for the options available when as is configured for a Meta processor.
See the info pages for documentation of the MMIX-specific options.
See NDS32 Options, for the options available when as is configured for a NDS32 processor.
See PowerPC-Opts, for the options available when as is configured for a PowerPC processor.
See RISC-V-Options, for the options available when as is configured for a RISC-V processor.
See the info pages for documentation of the RX-specific options.
The following options are available when as is configured for the s390 processor family.
Select the word size, either 31/32 bits or 64 bits.
Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
Specify which s390 processor variant is the target, ‘g5’ (or ‘arch3’), ‘g6’, ‘z900’ (or ‘arch5’), ‘z990’ (or ‘arch6’), ‘z9-109’, ‘z9-ec’ (or ‘arch7’), ‘z10’ (or ‘arch8’), ‘z196’ (or ‘arch9’), ‘zEC12’ (or ‘arch10’), ‘z13’ (or ‘arch11’), ‘z14’ (or ‘arch12’), or ‘z15’ (or ‘arch13’).
Allow or disallow symbolic names for registers.
Warn whenever the operand for a base or index register has been specified but evaluates to zero.
See TIC6X Options, for the options available when as is configured for a TMS320C6000 processor.
See TILE-Gx Options, for the options available when as is configured for a TILE-Gx processor.
See Visium Options, for the options available when as is configured for a Visium processor.
See Xtensa Options, for the options available when as is configured for an Xtensa processor.
See Z80 Options, for the options available when as is configured for an Z80 processor.
|• Manual||Structure of this Manual|
|• GNU Assembler||The GNU Assembler|
|• Object Formats||Object File Formats|
|• Command Line||Command Line|
|• Input Files||Input Files|
|• Object||Output (Object) File|
|• Errors||Error and Warning Messages|