The following code produces incorrect op-codes: @ start .syntax unified .thumb qadd r1,r2,r3 qdadd r1,r2,r3 qsub r1,r2,r3 qdsub r1,r2,r3 @ finish gas gives FA82F183 FA82F193 FA82F1A3 FA82F1B3 whereas it should give FA83F182 FA83F192 FA83F1A2 FA83F1B2
Subject: Bug 11013 CVSROOT: /cvs/src Module name: src Changes by: nickc@sourceware.org 2009-12-02 20:26:31 Modified files: gas : ChangeLog gas/config : tc-arm.c gas/testsuite : ChangeLog gas/testsuite/gas/arm: arch7em.d thumb32.d opcodes : ChangeLog arm-dis.c Log message: PR gas/11013 * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB and QDSUB. * gas/arm/arch7em.d: Update expected disassembly. * gas/arm/thumb32.d: Likewise. * config/tc-arm.c (do_t_simd2): New function. (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB. Patches: http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/ChangeLog.diff?cvsroot=src&r1=1.4033&r2=1.4034 http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/config/tc-arm.c.diff?cvsroot=src&r1=1.417&r2=1.418 http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1599&r2=1.1600 http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch7em.d.diff?cvsroot=src&r1=1.1&r2=1.2 http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb32.d.diff?cvsroot=src&r1=1.33&r2=1.34 http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1510&r2=1.1511 http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.114&r2=1.115
Created attachment 4441 [details] Fix encoding of saturated arithmatic instructions
Hi Anthony, Thanks for reporting this bug. We have checked in the uploaded patch to fix the problem. Please let us know if you encounter any further problems with the ARM assembler. Cheers Nick